Abstract: A voltage regulator and a corresponding method of regulating a voltage are presented. The voltage regulator includes an N-type power switch, an error amplifier, and a switch capacitor circuit. The switch capacitor circuit includes a first capacitor coupled to a network of switches, the switch capacitor circuit has a first port coupled to an output the error amplifier, a second port coupled to an output terminal of the power switch, and a third port coupled to a control terminal of the power switch. The switch capacitor circuit is iteratively operable between a first phase and a second phase. In the first phase the first port is coupled to ground via a path comprising the first capacitor, and in the second phase the second port is coupled to the third port via a path comprising the first capacitor. The voltage regulator may be implemented as a low dropout regulator.

Abstract: A Low Dropout Regulator (LDO) with Less Quiescent Current in the Dropout Region is described, including an error amplifier configured to compare a reference voltage to an LDO output voltage across a resistive divider, a current mirror configured to mirror a first output of the error amplifier to a first and second output of the current mirror, and a comparator configured to compare the LDO output voltage to a second output of the error amplifier, which has been compared to the second output of the current mirror, and configured to output a control voltage to the error amplifier, where a low quiescent current is maintained when an LDO input voltage is near or less than the LDO output voltage.

Abstract: A Low Dropout Regulator (LDO) with Less Quiescent Current in the Dropout Region is described, including an error amplifier configured to compare a reference voltage to an LDO output voltage across a resistive divider, a current mirror configured to mirror a first output of the error amplifier to a first and second output of the current mirror, and a comparator configured to compare the LDO output voltage to a second output of the error amplifier, which has been compared to the second output of the current mirror, and configured to output a control voltage to the error amplifier, where a low quiescent current is maintained when an LDO input voltage is near or less than the LDO output voltage.

Abstract: A voltage generator and a method for generating an output voltage is presented. The generator has a current mirror circuit with a first transistor having a gate and a first terminal, and a second transistor having a gate coupled to the gate of the first transistor, and with a first terminal coupled to a feedback node. A third transistor has a gate, a first terminal and a second terminal. The first terminal is coupled to the feedback node and the second terminal is coupled to an output node. A fourth transistor has a gate coupled to the third transistor. There is a current source coupled to the output node, and a feedback circuit to detect a terminal voltage at the feedback node and to control the terminal voltage by adjusting a gate voltage at the gate of the second transistor.

Abstract: A high precision voltage reference circuit is disclosed which replaces two current bias sources, with a single current mirror. Curvature-error correction is established with a modified current mirror circuit. Another object of this disclosure is the addition of a MOSFET device, to alleviate the output voltage variation, due to the channel modulation effect of the origin of the voltage reference.

Abstract: A high precision voltage reference circuit is disclosed which replaces two current bias sources, with a single current mirror. Curvature-error correction is established with a modified current mirror circuit. Another object of this disclosure is the addition of a MOSFET device, to alleviate the output voltage variation, due to the channel modulation effect of the origin of the voltage reference.

Abstract: A preferred implementation of a switching converter with a versatile current sensor is achieved, by adding an integrator for instant sense current in the switching converter. The integrator calculates the average current of the switching converter and includes both positive and negative current sensing. The current sensor's response time is determined by the integrator coefficient and therefore not limited by the bandwidth of the current sensor. Performance degradation in the current sensor due to offset current is removed and the current sensor does not require a voltage reference or a current reference. High accuracy current monitoring and current sensing is achieved without an external sense device. The integrator of the current sensor serves to boost the gain of the switching converter.

Abstract: A preferred implementation of a switching converter with a versatile current sensor is achieved, by adding an integrator for instant sense current in the switching converter. The integrator calculates the average current of the switching converter and includes both positive and negative current sensing. The current sensor's response time is determined by the integrator coefficient and therefore not limited by the bandwidth of the current sensor. Performance degradation in the current sensor due to offset current is removed and the current sensor does not require a voltage reference or a current reference. High accuracy current monitoring and current sensing is achieved without an external sense device. The integrator of the current sensor serves to boost the gain of the switching converter.

Abstract: An apparatus and method for a voltage reference circuit with improved precision. The voltage reference circuit utilizes threshold voltage difference between a pair of MOSFETs. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage, includes a first current mirror with a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor threshold voltage is not equal to said second NMOS transistor threshold voltage, a second current mirror with a first PMOS transistor, a second and third PMOS transistor configured to be coupled to said power supply node, a current source configured to be provide current to said second current mirror, an amplifier configured with a first and second input configured to be connected to the drains of said first NMOS transistor and said second NMOS transistor and, a feedback loop configured to be the output of said amplifier.

Abstract: A voltage-controlled oscillator 3 is constructed with a ring oscillator control circuit 2 and a ring oscillator 1, which is constructed with a plurality of differential amplifiers 5 to 8 each including a differential pair of transistors 24 and 25 and load circuits 22 and 23 connected to the respective transistors. The load circuits 22 and 23 are constructed such that the differential amplifiers always operate in linear region according to load drive voltages CL1 and CL2.

Abstract: A PLL circuit includes a comparator, an integrator, a phase controller, a current control oscillator and a feedback frequency divider. The comparator compares a phase of an input signal with a phase of a feedback signal to generate a comparison result. The integrator generates a first current to control an oscillation frequency of an output signal based on the comparison result. The phase controller controls a phase of the output signal based on the comparison result such that a phase difference between the phase of the input signal and the phase of the output signal at a lock state is reduced to generate a second current. The current control oscillator generates the output signal. The output signal oscillates at a frequency corresponding to a third current, wherein the first current and the second current add up to the third current. The feedback frequency divider performs a frequency division on the output signal to generate the feedback signal to send to the comparator.

Abstract: A charge pump circuit for a PLL includes first and second constant current sources, first and second current mirror circuits, and first and second analog switch circuits. The first and second constant current sources generate constant currents. The first current mirror circuit supplies a constant current having a value corresponding to the constant current generated by the first constant current source to an output terminal. The first current mirror circuit has a first transistor connected to the first constant current source and a second transistor connected to the output terminal. The second current mirror circuit supplies a constant current having a value corresponding to the constant current generated by the second constant current source to the output terminal. The second current mirror circuit has a third transistor connected to the second constant current source and a fourth transistor connected to the output terminal.

Abstract: A supply-voltage detector having a low minimum operational voltage while having a large variation is combined with a supply-voltage detector having a high detection precision while having a high minimum operational voltage, so that the supply voltage is detected at a high accuracy without malfunctioning even on a low voltage. A system, such as a microcomputer, could then be reset when the detected supply voltage falls below a certain value. This combined circuit will improve the accuracy of detecting this supply voltage.

Abstract: A digital-to-analog converting unit fabricated on a single semiconductor chip comprises a string of resistive elements coupled between a source of power voltage level and a source of ground voltage level and an array of switching elements respectively associated with intermediate nodes each provided between every adjacent two resistive elements, and each of the switching elements is implemented by a parallel combination of an n-channel type component field effect transistor and a p-channel type component field effect transistor even if one of the component field effect transistors of the switching elements near the voltage sources remains off at all times, because the parallel combinations enhances uniformity of pattern on the semiconductor chip, thereby preventing the string of the resistive elements from irregularity of sheet resistance.