Patents by Inventor Susumu Tominaga

Susumu Tominaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085278
    Abstract: According to one embodiment, an anomaly detection apparatus includes a processing circuit. The processing circuit is configured to: acquire measured values from sensors installed in a system, a first function, a first threshold, and a second function to output a second threshold; generate the predicted values based on the measured value and the first function; detect that a deviation between the measured values and the predicted values exceeds the first threshold; calculate the feature quantities based on the measured values; and determine whether a number of consecutive times is equal to or larger than the second threshold to detect an anomaly or a sign of the anomaly.
    Type: Application
    Filed: February 24, 2023
    Publication date: March 14, 2024
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Energy Systems & Solutions Corporation
    Inventors: Yasunori TAGUCHI, Kouta NAKATA, Susumu NAITO, Yuichi KATO, Shinya TOMINAGA, Naoyuki TAKADO, Ryota MIYAKE, Yusuke TERAKADO, Toshio AOKI
  • Patent number: 8135010
    Abstract: A communication system includes a station-side terminal apparatus and multiple subscriber-side terminal apparatuses connected to the station-side terminal apparatus. The station-side terminal apparatus is configured to, in response to receipt of a packet from a subscriber-side terminal apparatus, a packet indicating whether data distribution is required, identify the subscriber-side terminal apparatus that has transmitted the packet, and transmit a packet indicating an address for which whether the transfer of distribution data is required is designated to the subscriber-side terminal apparatus based on whether data distribution is required.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: March 13, 2012
    Assignee: Fujitsu Limited
    Inventors: Ikutaro Tsujikado, Masataka Yamada, Toshihiko Inoue, Hiroomi Shinha, Hajime Fukushima, Tetsumi Ichikawa, Shiro Mori, Osamu Sekihata, Susumu Tominaga
  • Patent number: 7418009
    Abstract: A method of communicating through a passive optical network (PON) that improves the efficiency of the network with low cost child apparatuses having only simple functions. A parent apparatus provides the child apparatuses with a multi-frame standard signal, and a child apparatus transfers asynchronous information as a frame of variable length, as it is, at a time delayed from the multi-frame standard signal by a time period designated by the parent apparatus. Since the asynchronous information does not need to be divided into pieces to which a frame header is attached, the efficiency of the uplink channel is increased.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: Susumu Tominaga, Masaharu Matsumoto, Takamitsu Shirai, Katsuhiko Hirashima, Kazuhiro Uchida, Kenichi Abe, Shigeharu Murakami, Miho Kawai, Kiyotaka Shikata
  • Publication number: 20050220104
    Abstract: A communication system includes a station-side terminal apparatus and multiple subscriber-side terminal apparatuses connected to the station-side terminal apparatus. The station-side terminal apparatus is configured to, in response to receipt of a packet from a subscriber-side terminal apparatus, a packet indicating whether data distribution is required, identify the subscriber-side terminal apparatus that has transmitted the packet, and transmit a packet indicating an address for which whether the transfer of distribution data is required is designated to the subscriber-side terminal apparatus based on whether data distribution is required.
    Type: Application
    Filed: March 24, 2005
    Publication date: October 6, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Ikutaro Tsujikado, Masataka Yamada, Toshihiko Inoue, Hiroomi Shinha, Hajime Fukushima, Tetsumi Ichikawa, Shiro Mori, Osamu Sekihata, Susumu Tominaga
  • Publication number: 20050058071
    Abstract: An optical access system that sends packets in a given time slot more efficiently without wasting bandwidth. The uplink channel from slave devices to a master device is divided into time slots. The sending slave device reads out upstream packets from its send packet buffer when an assigned time slot comes. If the maximum frame size is reached in the middle of a packet, the slave device suspends further reading until a next assigned time slot comes. The packets are sent to the master device, each being set off by a start and end delimiters. Detection of a start delimiter causes the master device to begin writing each received data word into a receive packet buffer, which is terminated by the end delimiter of that packet. Received packets are retrieved from their memory locations specified by a read address that includes the sender's slave device number.
    Type: Application
    Filed: December 3, 2003
    Publication date: March 17, 2005
    Inventors: Katsuhiko Hirashima, Kazuhiro Uchida, Masamichi Kasa, Susumu Tominaga
  • Publication number: 20030095568
    Abstract: A method of communicating through a passive optical network (PON) that improves the efficiency of the network with low cost child apparatuses having only simple functions. A parent apparatus provides the child apparatuses with a multi-frame standard signal, and a child apparatus transfers asynchronous information as a frame of variable length, as it is, at a time delayed from the multi-frame standard signal by a time period designated by the parent apparatus. Since the asynchronous information does not need to be divided into pieces to which a frame header is attached, the efficiency of the uplink channel is increased.
    Type: Application
    Filed: April 30, 2002
    Publication date: May 22, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Susumu Tominaga, Masaharu Matsumoto, Takamitsu Shirai, Katsuhiko Hirashima, Kazuhiro Uchida, Kenichi Abe, Shigeharu Murakami, Miho Kawai, Kiyotaka Shikata
  • Patent number: 6137795
    Abstract: A plurality of cell switches that operate at a basic switching rate are provided, and a unit including (FIFO buffers) for queuing cells from the transmission line are provided in correspondence with respective ones of the cell switches. Cells from the transmission line are demultiplexed and written to the prescribed FIFO buffer by a cell demultiplexer, cells are read out of each FIFO buffer at the basic switching rate and entered into the corresponding cell switch, and cells switched by each of the cell switches are multiplexed and sent to a transmission line by a multiplexer.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: October 24, 2000
    Assignee: Fujitsu Limited
    Inventors: Susumu Tominaga, Shinji Michii
  • Patent number: 5982296
    Abstract: A plurality of modules, each connected to communication lines, are interconnected by a logically separated interprocessor communication bus for transferring header information and control information and a frame transfer bus for transferring data. When each module receives data from a line, the module generates a header containing header information from the received data, stores the header and user data in respective queue-type data storage sections, and transmits the header on the interprocessor communication bus; when one of the other modules detects its own identification from the header on the bus, the module sends a data send request to the transmitting module which in response reads the data from the data storage and outputs it on the frame transfer bus for transmission to the requesting module.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: November 9, 1999
    Assignee: Fujitsu Limited
    Inventors: Shinji Wakasa, Susumu Tominaga
  • Patent number: 5309431
    Abstract: In a network, a route which can be uniquely identified is constructed by selecting an arbitrary packet-switching node and an arbitrary transmission line in an arbitrary order from the network. A route memory unit stores data indicating which route is involved in which transmission line within the network. A congested state detecting unit detects a congested state of a transmission line accommodated within its own node. The detected congested state is transmitted to another node by a congested state informing unit as congested state information. A route identifying unit receives the congested state information from the other node and retrieves a route within a corresponding transmission line from the route memory unit to thereby identify the route accommodated within its node. A route control unit carries out control of the congested state of the identified route on the basis of the received congested state information.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: May 3, 1994
    Assignee: Fujitsu Limited
    Inventors: Susumu Tominaga, Satoshi Nojima
  • Patent number: 5140582
    Abstract: A packet switching system having a matrix switch including input packet transfer buses and output packet transfer buses. Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.
    Type: Grant
    Filed: April 30, 1991
    Date of Patent: August 18, 1992
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Tsuboi, Susumu Tominaga, Akira Takeyama, Satoshi Nojima