Patents by Inventor Susumu Tsukimoto
Susumu Tsukimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110121459Abstract: Provided is a semiconductor interconnection wherein a barrier layer different from a TiO2 layer is formed on an interface between an insulating film and a Cu interconnection without increasing electrical resistivity of the Cu interconnection. In the semiconductor interconnection, a Cu interconnection containing Ti is embedded in a trench arranged on an insulating film on the semiconductor substrate, and a TiC layer is formed between the insulating film and the Cu interconnection. The insulating film is preferably composed of SiCO or SiCN. The thickness of the TiC layer is preferably 3-30 nm.Type: ApplicationFiled: July 10, 2009Publication date: May 26, 2011Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)Inventors: Takashi Onishi, Masao Mizuno, Hirotaka Ito, Kazuyuki Kohama, Kazuhiro Ito, Susumu Tsukimoto, Masanori Murakami
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Patent number: 7781339Abstract: A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 ?m or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.Type: GrantFiled: June 19, 2007Date of Patent: August 24, 2010Assignee: Kobe Steel, Ltd.Inventors: Takashi Onishi, Mikako Takeda, Masao Mizuno, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Patent number: 7572652Abstract: A light emitting element having a light emitting element portion formed of a group III nitride-based compound semiconductor and having a layer to emit light. The light emitting element portion is formed by lifting off a substrate by wet etching after the light emitting element portion is grown on the substrate. The light emitting element portion has a lift-off surface that is kept substantially intact as it is formed in growing the light emitting element portion on the substrate.Type: GrantFiled: February 21, 2007Date of Patent: August 11, 2009Assignee: Toyoda Gosei Co., Ltd.Inventors: Yuhei Ikemoto, Koji Hirata, Kazuhiro Ito, Yu Uchida, Susumu Tsukimoto, Masanori Murakami
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Patent number: 7550782Abstract: In a semiconductor device in which a group III nitride compound semiconductor layer is formed without a low temperature grown buffer layer provided on an undercoat layer formed by a metal nitride layer, the metal nitride layer is formed of reddish brown titanium nitride. The reddish brown titanium nitride can be obtained by causing nitrogen to be rich in the titanium nitride.Type: GrantFiled: September 23, 2005Date of Patent: June 23, 2009Assignee: Toyoda Gosei Co., Ltd.Inventors: Masanori Murakami, Teppei Watanabe, Susumu Tsukimoto, Kazuhiro Ito, Jun Ito, Miki Moriyama, Naoki Shibata
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Patent number: 7538027Abstract: There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 ?m, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C.Type: GrantFiled: September 18, 2006Date of Patent: May 26, 2009Assignee: Kobe Steel, Ltd.Inventors: Takashi Onishi, Masao Mizuno, Mikako Takeda, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Publication number: 20080014743Abstract: A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 ?m or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.Type: ApplicationFiled: June 19, 2007Publication date: January 17, 2008Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)Inventors: Takashi Onishi, Mikako Takeda, Masao Mizuno, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Publication number: 20070218690Abstract: There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 ?m, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C.Type: ApplicationFiled: September 18, 2006Publication date: September 20, 2007Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)Inventors: Takashi Onishi, Masao Mizuno, Mikako Takeda, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Publication number: 20070210320Abstract: A light emitting element having a light emitting element portion formed of a group III nitride-based compound semiconductor and having a layer to emit light. The light emitting element portion is formed by lifting off a substrate by wet etching after the light emitting element portion is grown on the substrate. The light emitting element portion has a lift-off surface that is kept substantially intact as it is formed in growing the light emitting element portion on the substrate.Type: ApplicationFiled: February 21, 2007Publication date: September 13, 2007Applicant: TOYODA GOSEI CO., LTD.Inventors: Yuhei Ikemoto, Koji Hirata, Kazuhiro Ito, Yu Uchida, Susumu Tsukimoto, Masanori Murakami
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Publication number: 20060065898Abstract: In a semiconductor device in which a group III nitride compound semiconductor layer is formed without a low temperature grown buffer layer provided on an undercoat layer formed by a metal nitride layer, the metal nitride layer is formed of reddish brown titanium nitride. The reddish brown titanium nitride can be obtained by causing nitrogen to be rich in the titanium nitride.Type: ApplicationFiled: September 23, 2005Publication date: March 30, 2006Applicant: Toyoda Gosei Co., Ltd.Inventors: Masanori Murakami, Teppei Watanabe, Susumu Tsukimoto, Kazuhiro Ito, Jun Ito, Miki Moriyama, Naoki Shibata