Patents by Inventor Sutee Vongfuangfoo

Sutee Vongfuangfoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6126063
    Abstract: Apparatus and method for assembling solder balls in a selected one of several different patterns for delivery to connector pads on an integrated circuit package, or other receiver, includes a universal template containing holes at locations in an aggregate pattern of all hole locations for the several different patterns, and includes a subtemplate for each individual different pattern that contains posts at locations for insertion from the rear of the template into holes therein at locations where no surface recess is desired. The universal template may remain aligned with an assembly jig or holder of packages while only the subtemplate is changed to change the surface pattern of holes into which solder balls may then be distributed.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: October 3, 2000
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Minh Vuong, Brent R. Bacher
  • Patent number: 5972738
    Abstract: A PBGA package includes PBGA member, a stiffener ring, and a stiffener fixture which includes a retaining recess having a floor for receiving the stiffener ring and includes a ledge positioned above the recess floor for receiving the PBGA member. An adhesive layer is applied to the stiffener ring, which is adhered to the PBGA member. The stiffener ring and PBGA member are essentially coplanar to less than 8 mils. A top plate is placed on top of the PBGA member and the ring and member are secured together tightly.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: October 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Brent Bacher, Felipe Sumagaysay
  • Patent number: 5716493
    Abstract: A lid is sealed to an integrated circuit package using a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The secondary jig attaches to the fabrication boat at a position indexed to apply optimal assembly force at the package center normal of the package lid plane.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: February 10, 1998
    Inventors: Sutee Vongfuangfoo, Mirek Boruta, Galen Kirkpatrick
  • Patent number: 5695593
    Abstract: A lid is sealed to an integrated circuit package by a method that uses a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The pressure foot is retracted against the spring bias while secondary jig index pins are meshed with corresponding sockets in the fabrication boat that are aligned with the package position on the boat. When the pins and sockets are meshed, the pressure foot is released to apply optimal assembly force at the package center normal of the package lid plane.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: December 9, 1997
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Mirek Boruta, Galen Kirkpatrick
  • Patent number: 5632437
    Abstract: A lid is sealed to an integrated circuit package by a method that uses a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The pressure foot is retracted against the spring bias while secondary jig index pins are meshed with corresponding sockets in the fabrication boat that are aligned with the package position on the boat. When the pins and sockets are meshed, the pressure foot is released to apply optimal assembly force at the package center normal of the package lid plane.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: May 27, 1997
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Mirek Boruta, Galen Kirkpatrick
  • Patent number: 5598775
    Abstract: A lid is sealed to an integrated circuit package using a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The secondary jig attaches to the fabrication boat at a position indexed to apply optimal assembly force at the package center normal of the package lid plane.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: February 4, 1997
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Mirek Boruta, Galen Kirkpatrick
  • Patent number: 5465470
    Abstract: A fixture clamps a plurality of lids onto a multi-chip module (MCM) integrated circuit for adhesively attaching the lids to cover a plurality of cavities in the module in which chips or dies are mounted. The fixture includes a base plate which is formed with recesses in which the lids and the module are fittingly retained with the lids properly positioned relative to the module. A pressure plate is guided onto the module by a pin assembly and presses the module against the base plate. A plurality of spring loaded clamps have first jaws that engage with the lids through respective holes in the base plate and second jaws that engage with the pressure plate. The clamp thereby clamps the lids and the pressure plate to the module. The assembly including the module, lids, pressure plate and clamps is then removed from the base plate to enable curing of an adhesive that bonds the lids to the module, and frees the base plate for reuse.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: November 14, 1995
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Robert Trabucco
  • Patent number: 5392932
    Abstract: A boat transport is fabricated to receive either pins-down or pins-up type semiconductor device assemblies, without damaging the pins, and to position the body of the semiconductor device assembly for subsequent packaging processes. The boat transport includes a planar platform for supporting a peripheral portion of the package body. A single large cutout through the platform receives all of the pins of the semiconductor device assembly. Guides which extend downward from the platform along each side (edge) of the cutout prevent lateral and rotational movement of a pins-down package. Other guides, which ascend upward from the platform along each side (edge) of the cut out, prevent pins-up packages from lateral and rotational movement. Additional cutouts through the platform accommodate chip capacitors.
    Type: Grant
    Filed: December 24, 1992
    Date of Patent: February 28, 1995
    Assignee: LSI Logic Corporation
    Inventor: Sutee Vongfuangfoo
  • Patent number: 5278447
    Abstract: Damage to the package body and external leads of a leaded semiconductor device assembly is prevented by a carrier assembly. The carrier assembly includes a rigid bottom (lower) plate positively supporting the package body and providing a bottom cover for the external leads. A semi-rigid top (upper) plate positively holds the package body against the bottom plate, prevents movement of the package body with respect to the carrier assembly, and covers the external leads. Fasteners are provided for securing the upper plate to the lower plate, preferably at the four corners of the plates. In this manner, a durable "sandwich" structure is created, with the package disposed between the lower and upper plates and the body and leads well protected against damage.
    Type: Grant
    Filed: January 16, 1992
    Date of Patent: January 11, 1994
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Matthew Preston