Abstract: In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.

Abstract: The present disclosure provides an adaptive shading correction method for correcting an image for lens shading, including segmenting the image into a plurality of blocks of pixels and identifying hue-flat blocks with a relatively low hue variance, where the hue-flat blocks are clustered into at least one cluster based on a spatial distribution of the blocks. Selected modification parameters for modifying an average shading mesh are identified by modifying the average shading mesh along a plurality of dimensions using a plurality of modification parameters, and processing the at least one cluster with the average shading mesh as modified so as to identify the selected modification parameters. The average shading mesh is modified using the selected modification parameters to generate a shading correction mesh, which is used to correct the image for lens shading.

Abstract: In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.

Abstract: In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.

Abstract: The present disclosure provides an adaptive shading correction method for correcting an image for lens shading, including segmenting the image into a plurality of blocks of pixels and identifying hue-flat blocks with a relatively low hue variance, where the hue-flat blocks are clustered into at least one cluster based on a spatial distribution of the blocks. Selected modification parameters for modifying an average shading mesh are identified by modifying the average shading mesh along a plurality of dimensions using a plurality of modification parameters, and processing the at least one cluster with the average shading mesh as modified so as to identify the selected modification parameters. The average shading mesh is modified using the selected modification parameters to generate a shading correction mesh, which is used to correct the image for lens shading.

Abstract: In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.

Abstract: In a video application, a method and system provide different sizes of data-fetch where the data transfer rate between a decoder and an external memory (e.g., DDR memory) is extremely high, as for example in HDTV systems. The invention in one form divides a reference frame into different tiles where each tile is hierarchically divided into smaller tiles to a level where the minimum tile size is the same as the fixed burst size of the DDR memory. The method also provides for arranging the biggest tiles into different banks and pages so that even if the block to be fetched falls across tile boundaries, the latency penalty in the tile transition will be minimized. The invention provides advantages also for progressive and interlaced data fetch.

Abstract: In a video application, a method and system provide different sizes of data-fetch where the data transfer rate between a decoder and an external memory (e.g., DDR memory) is extremely high, as for example in HDTV systems. The invention in one form divides a reference frame into different tiles where each tile is hierarchically divided into smaller tiles to a level where the minimum tile size is the same as the fixed burst size of the DDR memory. The method also provides for arranging the biggest tiles into different banks and pages so that even if the block to be fetched falls across tile boundaries, the latency penalty in the tile transition will be minimized. The invention provides advantages also for progressive and interlaced data fetch.