Patents by Inventor Sutirtha Kabir

Sutirtha Kabir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10997333
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 4, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Balvinder Singh, Arnold Jean Marie Gustave Ginetti, Sutirtha Kabir, Diwakar Mohan, Madhur Sharma
  • Patent number: 10909302
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing electronic designs with electronic design simplification techniques. These techniques identify an input for simplifying an electronic design and generates a simplified electronic design at least by performing layout simplification on the electronic design. A characterization input may be determined for subsequent characterization of the simplified electronic design. An electromagnetic behavior of the simplified electronic design may then be characterized using at least the characterization input.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 2, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Jean Marie Gustave Ginetti, Steve Song Lee, Sutirtha Kabir, Jean-Noel Francois Philippe Marie Pic, Xavier Alasseur
  • Patent number: 10706206
    Abstract: A computer may generate a record of a template associated with a schematic design corresponding to an integrated circuit design. The template may have one or more instances corresponding to one or more initial parameters associated with a chain of one or more transmission line components of the integrated circuit design. The computer may then modify content of the chain of one or more transmission line components in a circuit layout corresponding to the schematic design within the maximum range limit of the one or more initial parameters. The computer may update the one or more instances according to modified contents of the one or more transmission line components in the circuit layout.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sutirtha Kabir, Vishal Agarwal, Reenee Raizada Tayal