Abstract: Circuits and systems include a parallel resistor-capacitor (RC) network coupled between a pin and ground, and first and second transistors coupled in source follower configuration with a common gate coupling. The source of the first transistor is coupled to the pin. A first switch couples a drain of the first transistor to the common gate coupling during soft-start (SS) and decouples that connection during over current limit (OCL) sensing, and a second switch couples a drain of the second transistor to the common gate coupling during OCL sensing and decouples that connection during SS. A first current source is enabled deliver a constant current to the pin during SS. A second current source is enabled to generate a reference voltage at the source of the second transistor during OCL, which reference voltage is transferred to the pin by the source follower configuration. A comparator controls the switches to transition from SS to OCL sensing.

Abstract: In described examples, a converter circuit includes a primary-side ground, a current sensor, a control signal generator, first and second control switches, and a transformer with a center-tapped primary-side coil. A first terminal of the first control switch is coupled to a first terminal of the coil and a first input of the current sensor. A first terminal of the second control switch is coupled to a second terminal of the coil and a second input of the current sensor. Second terminals of the first and second control switches are coupled to ground. The control signal generator closes the first control switch and opens the second control switch in a first phase; opens the first control switch and closes the second control switch in a second phase that alternates with the first phase; and adjusts first phase duration in response to current sensor output, without changing converter period duration.

Abstract: A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.

Abstract: An example apparatus includes: a current mirror having first and second outputs; oscillator circuitry including: a first transistor having a first terminal coupled to the first output of the current mirror, having a second terminal, and having a control terminal; and a second transistor having a first terminal coupled to the first output of the current mirror, having a second terminal coupled to the control terminal and the second terminal of the first transistor, and having a control terminal coupled to the second terminals of the first and second transistors; and current shunt circuitry having a terminal coupled to the second output of the current mirror.

Abstract: A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

Abstract: Circuits and systems include a parallel resistor-capacitor (RC) network coupled between a pin and ground, and first and second transistors coupled in source follower configuration with a common gate coupling. The source of the first transistor is coupled to the pin. A first switch couples a drain of the first transistor to the common gate coupling during soft-start (SS) and decouples that connection during over current limit (OCL) sensing, and a second switch couples a drain of the second transistor to the common gate coupling during OCL sensing and decouples that connection during SS. A first current source is enabled deliver a constant current to the pin during SS. A second current source is enabled to generate a reference voltage at the source of the second transistor during OCL, which reference voltage is transferred to the pin by the source follower configuration. A comparator controls the switches to transition from SS to OCL sensing.

Abstract: A system includes a switching converter, an input voltage source coupled to an input of the switching converter, and a load coupled to an output of the switching converter. The system also includes a load sense circuit coupled to the load and configured to provide a load sense signal. The system also includes an oscillator coupled to the switching converter and configured to provide a spread spectrum modulated (SSM) clock signal to the switching converter, wherein a frequency of the SSM clock signal varies as a function of the load sense signal.

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

Abstract: An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator.

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

Abstract: DC-DC power converter architecture is disclosed. In an example, an integrated circuit includes an H-bridge switching circuit operatively coupled with a transformer. The switching circuit is compensated to account for parasitic differences between the high-side (power) and low-side (ground). For instance, PMOS transistors connected to the high-side are sized larger to substantially match on-resistance of NMOS transistors connected to the low-side (e.g., such that the on-resistances are all within a tolerance of one another, or within a tolerance of a target on-resistance value), and the NMOS transistors include additional gate-drain capacitance to substantially match gate-drain capacitance of the larger PMOS transistors (e.g., such that the gate-drain capacitances are all within a tolerance of one another, or within a tolerance of a target gate-drain capacitance value).

Abstract: An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator.

Abstract: A system includes a switching converter, an input voltage source coupled to an input of the switching converter, and a load coupled to an output of the switching converter. The system also includes a load sense circuit coupled to the load and configured to provide a load sense signal. The system also includes an oscillator coupled to the switching converter and configured to provide a spread spectrum modulated (SSM) clock signal to the switching converter, wherein a frequency of the SSM clock signal varies as a function of the load sense signal.