Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processor. The apparatus may allocate a memory location in a plurality of memory locations for data for each of a plurality of threads. The apparatus may also align the data for each of the plurality of threads with the allocated memory location if the data is not aligned with the allocated memory location; or refrain from aligning the data for each of the plurality of threads with the allocated memory location if the data is aligned with the allocated memory location. Further, the apparatus may output an indication of the aligned data for each of the plurality of threads or the refrained from aligned data for each of the plurality of threads.

Abstract: Efficiently handling restart indices during tile-based deferred rendering (TBDR) by graphics processing units (GPUs) is disclosed herein. In some aspects, a processor circuit of a GPU determines, during a tile sorting pass, a location of a restart index in a plurality of indices of an index buffer associated with a primitive topology, and determines a skip count indicating a number of indices to skip during a tile rendering pass, based on the primitive topology and the location of the restart index. In some aspects, the processor circuit also determines visibility statuses corresponding to primitives of the primitive topology, and generates visibility data comprising the visibility statuses and the skip count. Subsequently, during the tile rendering pass, the processor circuit bypasses fetching of the restart index, based on the skip count. According to some aspects, the processor circuit may also assemble the primitives based on the visibility data.

Abstract: Efficiently handling restart indices during tile-based deferred rendering (TBDR) by graphics processing units (GPUs) is disclosed herein. In some aspects, a processor circuit of a GPU determines, during a tile sorting pass, a location of a restart index in a plurality of indices of an index buffer associated with a primitive topology, and determines a skip count indicating a number of indices to skip during a tile rendering pass, based on the primitive topology and the location of the restart index. In some aspects, the processor circuit also determines visibility statuses corresponding to primitives of the primitive topology, and generates visibility data comprising the visibility statuses and the skip count. Subsequently, during the tile rendering pass, the processor circuit bypasses fetching of the restart index, based on the skip count. According to some aspects, the processor circuit may also assemble the primitives based on the visibility data.

Abstract: The present disclosure relates to methods and apparatus for sharing GPU hardware to generate bin visibility information concurrently for graphics processing. The apparatus can cause a processor to: store, in a GMEM, first data associated with a first graphics processing pass for a first frame of graphics data and second data associated with a second graphics processing pass for a second frame of graphics data. The apparatus can also cause a geometry processor to perform the first graphics processing pass using the first data and a second processor to concurrently perform the second graphics processing pass using the second data such that the first graphics processing pass and the second graphics processing path share the geometry processor. In some aspects, the apparatus can switch the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. The apparatus can determine visibility information for each of a plurality of primitives in a first viewpoint or any available viewpoint of an image. In some aspects, the visibility information can include information regarding whether the primitive is visible in the first viewpoint. The apparatus can also determine a visibility stream based on the determined visibility information for each of the plurality of primitives in the first viewpoint. Additionally, the apparatus can identify at least one of the plurality of primitives in the first viewpoint as not visible based on the determined visibility information. The apparatus can also determine to skip rendering the plurality of primitives in the first viewpoint identified as not visible. Further, the apparatus can send and store the visibility stream in the buffer and retrieve the visibility stream from the buffer.