Patents by Inventor Suvam Nandi

Suvam Nandi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11509294
    Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: November 22, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Badarish Mohan Subbannavar, Arnab Khawas, Suvam Nandi
  • Publication number: 20210265985
    Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Inventors: Badarish Mohan SUBBANNAVAR, Arnab KHAWAS, Suvam NANDI
  • Patent number: 11043937
    Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: June 22, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Badarish Mohan Subbannavar, Arnab Khawas, Suvam Nandi
  • Publication number: 20210184659
    Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Badarish Mohan SUBBANNAVAR, Arnab KHAWAS, Suvam NANDI
  • Patent number: 11029919
    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 8, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
  • Publication number: 20200301666
    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
    Type: Application
    Filed: April 20, 2020
    Publication date: September 24, 2020
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
  • Patent number: 10666293
    Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Jaiganesh Balakrishnan
  • Patent number: 10635396
    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
  • Publication number: 20190319612
    Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Inventors: Suvam Nandi, Badarish Mohan Subbannavar
  • Publication number: 20190317731
    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
  • Patent number: 10396829
    Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 27, 2019
    Assignee: TEXAS INTSTUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
  • Patent number: 10382020
    Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suvam Nandi, Badarish Mohan Subbannavar
  • Patent number: 10372415
    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Pooja Sundar, Jaiganesh Balakrishnan
  • Publication number: 20180367169
    Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
  • Publication number: 20180331675
    Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Inventors: Suvam Nandi, Badarish Mohan Subbannavar
  • Patent number: 10090866
    Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 2, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
  • Publication number: 20180241413
    Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Inventors: Jawaharlal TANGUDU, Suvam NANDI, Jaiganesh BALAKRISHNAN
  • Patent number: 10056882
    Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 21, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suvam Nandi, Badarish Mohan Subbannavar
  • Publication number: 20180191383
    Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
  • Patent number: 9985650
    Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 29, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jawaharlal Tangudu, Suvam Nandi, Jaiganesh Balakrishnan