Patents by Inventor Suvansh Krishan Kapur

Suvansh Krishan Kapur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for exploiting parallelism across multiple traffic streams through a single channel
    Patent number: 7562194
    Abstract: Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the relaxed ordering, essential programming paradigms such as producer-consumer relationships are not affected. Chipsets and systems using the methods are also described and claimed.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Raman Nayyar, Suvansh Krishan Kapur
  • Transaction flow and ordering for a packet processing engine, located within an input-output hub
    Patent number: 7487284
    Abstract: An apparatus and method for controlling data traffic flow and data ordering of packet data between one or more peripheral devices and a processor/memory combination by using a packet processing engine, located within an input-output hub (IOH). The IOH may include a packet processing engine, and a switch to route packet data between the one or more peripheral devices and the packet processing engine. The packet processing engine of the IOH may control data traffic flow and data ordering of the packet data to and from the one or more peripheral devices through the switch and also maintains flow and ordering to the processor/memory subsystem. The packet processing engine may be operable to perform packet processing operations, such as virtualization of a peripheral device or Transmission Control Protocol/Internet Protocol (TCP/IP) offload.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: February 3, 2009
    Assignee: Intel Corporation
    Inventors: Suvansh Krishan Kapur, Ali S. Oztaskin, Raman Nayyar
  • Transaction flow and ordering for a packet processing engine, located within an input-output hub
    Publication number: 20080025289
    Abstract: An apparatus and method for controlling data traffic flow and data ordering of packet data between one or more peripheral devices and a processor/memory combination by using a packet processing engine, located within an input-output hub (IOH). The IOH may include a packet processing engine, and a switch to route packet data between the one or more peripheral devices and the packet processing engine. The packet processing engine of the IOH may control data traffic flow and data ordering of the packet data to and from the one or more peripheral devices through the switch and also maintains flow and ordering to the processor/memory subsystem. The packet processing engine may be operable to perform packet processing operations, such as virtualization of a peripheral device or Transmission Control Protocol/Internet Protocol (TCP/IP) offload.
    Type: Application
    Filed: July 28, 2006
    Publication date: January 31, 2008
    Inventors: Suvansh Krishan Kapur, Ali S. Oztaskin, Raman Nayyar