Patents by Inventor Suvarna Harish Kumar

Suvarna Harish Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7173727
    Abstract: A computer implemented method of rasterizing a page in a page description language efficiently utilizes the resources of a multiprocessor integrated circuit by spawning of subtasks from a RISC type processor to one or more DSP type processors. The RISC type processor interprets the page in the page description language and detects a Y coordinate of edge intersection using the floating point calculation unit. The DSP type processors sort polygon edges in increasing Y coordinate and detect a Y coordinate of edge intersections via successive midpoint approximation using an integer multiplier unit.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: February 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sadhana Gupta, Suvarna Harish Kumar, Venkat V. Easwar, Arunabha Ghose
  • Publication number: 20040257607
    Abstract: A computer implemented method of clipping to a clip polygon and trapezoid formation employs an edge array rather than a set linked list from an array of pointers equal in number to the number of scan lines. This eliminates storage of linked list pointers which in the prior art included many null pointers resulting in better memory utilization. This method sorts the active edge table only at edge intersections and vertices, thus eliminating much unneeded sorting. This method permits integrated clipping of a subject polygon by a clip polygon and forming trapezoids filling the clipped area by activating trapezoid formation at every vertex of either polygon and at every edge intersection.
    Type: Application
    Filed: December 30, 2003
    Publication date: December 23, 2004
    Inventors: Sadhana Gupta, Suvarna Harish Kumar, Venkat V. Easwar, Arunabha Ghose
  • Publication number: 20040160627
    Abstract: This invention cures many inefficiencies with known scan conversion methods. This invention employs a edge array rather than a set linked list from an array of pointers equal in number to the number of scan lines. This invention thus eliminates storage of linked list pointers which in the prior art included many null pointers resulting in better memory utilization. es on-chip memory when employing a single chip microprocessor. This invention sorts the active edge table only at edge intersections and vertices, thus eliminating much unneeded sorting. This invention permits integrated clipping of a subject polygon by a clip polygon and forming trapezoids filling the clipped area by activating trapezoid formation at every vertex of either polygon and at every edge intersection. This process saves code space and computer processing time. This invention efficiently utilizes the resources of a multiprocessor integrated circuit by spawning of subtasks from a RISC type processor to one or more DSP type processors.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 19, 2004
    Inventors: Sadhana Gupta, Suvarna Harish Kumar, Venkat V. Easwar, Arunabha Ghose
  • Patent number: 6693719
    Abstract: This invention cures many inefficiencies with known scan conversion methods. This invention employs an edge array rather than a set linked list from an array of pointers equal in number to the number of scan lines. This invention thus eliminates storage of linked list pointers which in the prior art included many null pointers resulting in better memory utilization. This invention sorts the active edge table only at edge intersections and vertices, thus eliminating much unneeded sorting. This invention permits integrated clipping of a subject polygon by a clip polygon and forming trapezoids filling the clipped area by activating trapezoid formation at every vertex of either polygon and at every edge intersection. This process saves code space and computer processing time. This invention efficiently utilizes the resources of a multiprocessor integrated circuit by spawning of subtasks from a RISC type processor to one or more DSP type processors.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: February 17, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Sadhana Gupta, Suvarna Harish Kumar, Venkat V. Easwar, Arunabha Ghose
  • Patent number: 6567182
    Abstract: This invention cures many inefficiencies with known scan conversion methods. This invention employs a edge array rather than a set linked list from an array of pointers equal in number to the number of scan lines. This invention thus eliminates storage of linked list pointers which in the prior art included many null pointers resulting in better memory utilization. es on-chip memory when employing a single chip microprocessor. This invention sorts the active edge table only at edge intersections and vertices, thus eliminating much unneeded sorting. This invention permits integrated clipping of a subject polygon by a clip polygon and forming trapezoids filling the clipped area by activating trapezoid formation at every vertex of either polygon and at every edge intersection. This process saves code space and computer processing time. This invention efficiently utilizes the resources of a multiprocessor integrated circuit by spawning of subtasks from a RISC type processor to one or more DSP type processors.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: May 20, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Suvarna Harish Kumar, Sadhana Gupta, Lowell Boggs, Venkat V. Easwar, Arunabha Ghose
  • Patent number: 6288724
    Abstract: This invention cures many inefficiencies with known scan conversion methods. This invention employs a edge array rather than a set linked list from an array of pointers equal in number to the number of scan lines. This invention thus eliminates storage of linked list pointers which in the prior art included many null pointers resulting in better memory utilization. es on-chip memory when employing a single chip microprocessor. This invention sorts the active edge table only at edge intersections and vertices, thus eliminating much unneeded sorting. This invention permits integrated clipping of a subject polygon by a clip polygon and forming trapezoids filling the clipped area by activating trapezoid formation at every vertex of either polygon and at every edge intersection. This process saves code space and computer processing time. This invention efficiently utilizes the resources of a multiprocessor integrated circuit by spawning of subtasks from a RISC type processor to one or more DSP type processors.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: September 11, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Suvarna Harish Kumar, Venkat V. Easwar, Arunabha Ghose