Abstract: A computer trains, based on many timeseries, many anomaly detectors. Each anomaly detector is configured with a respective distinct contamination factor. Each timeseries is a temporal sequence of datapoints that characterize a device. Each datapoint in the many timeseries has a respective label that indicates whether the device failed when the datapoint occurred. Each anomaly detector detects: a set of anomalous datapoints, the size of which is proportional to the contamination factor of the anomaly detector, a healthy count of anomalous datapoints in timeseries of devices not failed, and an unhealthy count of anomalous datapoints in timeseries of failed devices. For a particular anomaly detector, the computer detects that the magnitude of the difference between the respective healthy count and the respective unhealthy count is less than a predefined threshold. Based on the contamination factor of the particular anomaly detector, anomalous datapoints are oversampled.

Abstract: A method and apparatus for correcting baseline wander is disclosed. The method and apparatus may include generating filtered signals by filtering input signals using a filter circuit. An equalizer circuit using the filtered signals may generate output signals. Feedback networks may be configured to couple a respective output signal to a corresponding filtered signal.

Abstract: The disclosed embodiments relate to the design of a temperature sensor, which is integrated into a semiconductor chip. This temperature sensor comprises an electro-thermal filter (ETF) integrated onto the semiconductor chip, wherein the ETF comprises: a heater; a thermopile, and a heat-transmission medium that couples the heater to the thermopile, wherein the heat-transmission medium comprises a polysilicon layer sandwiched between silicon dioxide layers. It also comprises a measurement circuit that measures a transfer function through the ETF to determine a temperature reading for the temperature sensor.

Abstract: We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

Abstract: A method and apparatus for correcting baseline wander is disclosed. The method and apparatus may include generating filtered signals by filtering input signals using a filter circuit. An equalizer circuit using the filtered signals may generate output signals. Feedback networks may be configured to couple a respective output signal to a corresponding filtered signal.

Abstract: We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

Abstract: During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator.

Abstract: An optical receiver receives a photocurrent from a photosensor and uses a transimpedance element to convert the photocurrent into an input voltage signal. An amplifier then amplifies the input voltage signal to produce a receiver output. During this process, a reference-voltage-generation circuit generates a reference voltage for the amplifier. This reference-voltage-generation circuit includes a data-detection circuit that detects data on the input voltage signal, and an adjustable low-pass filter, which filters the input voltage signal to produce the reference voltage. During a faster operating mode, which occurs when the data-detection circuit does not detect data on the input voltage signal, the filter has a cutoff frequency f1. During a slower operating mode, which starts a bias-delay time tBD after the data-detection circuit detects data on the input voltage signal, and lasts until the data-detection circuit no longer detects data, the filter has a lower cutoff frequency f2.

Abstract: An optical receiver receives a photocurrent from a photosensor and uses a transimpedance element to convert the photocurrent into an input signal. Next, an amplifier amplifies the input signal to produce an amplified input signal. At the same time, a clock-recovery circuit generates a clock signal, which is used to clock the amplified input signal to produce a receiver output. During an initial-calibration operation, the clock-recovery circuit phase-aligns a locally generated reference signal with transitions in the amplified input voltage signal to produce the clock signal by: feeding the reference signal through a delay-locked loop to produce a set of equally spaced phases; using the set of equally spaced phases to sample a preamble in the amplified input voltage signal to detect a crossing point; choosing a corresponding phase from the set of equally spaced phases based on the crossing point; and using the chosen phase to produce the clock signal.

Abstract: The disclosed embodiments relate to the design of a temperature sensor, which is integrated into a semiconductor chip. This temperature sensor comprises an electro-thermal filter (ETF) integrated onto the semiconductor chip, wherein the ETF comprises: a heater; a thermopile, and a heat-transmission medium that couples the heater to the thermopile, wherein the heat-transmission medium comprises a polysilicon layer sandwiched between silicon dioxide layers. It also comprises a measurement circuit that measures a transfer function through the ETF to determine a temperature reading for the temperature sensor.

Abstract: In an integrated circuit, a resettable data latch and a second resettable data latch at ends of a pipeline in a frequency-comparison circuit receive input clocks. This pipeline operates asynchronously and includes at least a pair of flow-control elements separated by a NAND-gate detector circuit. Moreover, the resettable data latch and the second resettable data latch selectively generate tokens and spaces based on rising or falling edges of the input clocks. Then, the frequency-comparison circuit moves the tokens and the spaces in the pipeline between the ends based on a difference in fundamental frequencies of the input clocks. Furthermore, arbiter circuits in the frequency-comparison circuit provide output signals based on changes in numbers of tokens proximate to the ends, to indicate how at least one of the input clocks should be adjusted so that the fundamental frequencies converge on a common value.

Abstract: A source-synchronization interface circuit includes: a sender synchronous-to-asynchronous protocol converter that receives sender data and a sender clock and that has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock; an asynchronous FIFO buffer with multiple stages that conveys phase information and data from the sender synchronous-to-asynchronous protocol converter to a receiver synchronous-to-asynchronous protocol converter; and a receiver synchronous-to-asynchronous protocol converter that receives the receiver clock and that has regenerative gain to resolve metastability during the phase synchronization.

Abstract: A source-synchronization interface circuit includes: a sender synchronous-to-asynchronous protocol converter that receives sender data and a sender clock and that has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock; an asynchronous FIFO buffer with multiple stages that conveys phase information and data from the sender synchronous-to-asynchronous protocol converter to a receiver synchronous-to-asynchronous protocol converter; and a receiver synchronous-to-asynchronous protocol converter that receives the receiver clock and that has regenerative gain to resolve metastability during the phase synchronization.

Abstract: A clock deskew circuit for transferring data from a first clock domain to a second clock domain. This circuit includes a data path, which has: a transmitter latch controlled by a transmitter clock in a first clock domain; a receiver latch controlled by a receiver clock in a second clock domain; and an intermediate latch coupled between the transmitter latch and the receiver latch. The transmitter clock and the receiver clock have an unknown phase offset. The circuit additionally includes a control circuit coupled between the transmitter clock and the receiver clock, and generates a control clock for the immediate latch based on the transmitter clock and the receiver clock. The control circuit selects between a first operation mode and a second operation mode for the data path circuit based at least on the phase relationship of the control clock with respect to the transmitter clock and the receiver clock.

Abstract: A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.

Abstract: The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

Abstract: The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.