Patents by Inventor Suyog Gupta
Suyog Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977974Abstract: A system, having a memory that stores computer executable components, and a processor that executes the computer executable components, reduces data size in connection with training a neural network by exploiting spatial locality to weight matrices and effecting frequency transformation and compression. A receiving component receives neural network data in the form of a compressed frequency-domain weight matrix. A segmentation component segments the initial weight matrix into original sub-components, wherein respective original sub-components have spatial weights. A sampling component applies a generalized weight distribution to the respective original sub-components to generate respective normalized sub-components. A transform component applies a transform to the respective normalized sub-components.Type: GrantFiled: November 30, 2017Date of Patent: May 7, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Suyog Gupta, Pritish Narayanan
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Publication number: 20230418677Abstract: The present disclosure describes a system and method for preempting a long-running process with a higher priority process in a machine learning system, such as a hardware accelerator. The machine learning hardware accelerator can be a multi-chip system including semiconductor chips that can be application-specific integrated circuits (ASIC) designed to perform machine learning operations. An ASIC is an integrated circuit (IC) that is customized for a particular use.Type: ApplicationFiled: December 21, 2020Publication date: December 28, 2023Inventors: Temitayo Fadelu, Ravi Narayanaswami, JiHong Min, Dongdong Li, Suyog Gupta, Jason Jong Kyu Park
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Publication number: 20220300421Abstract: Components on an IC chip may operate faster or provide higher performance relative to power consumption if allowed access to sufficient memory resources. If every component is provided its own memory, however, the chip becomes expensive. In described implementations, memory is shared between two or more components. For example, a processing component can include computational circuitry and a memory coupled thereto. A multi-component cache controller is coupled to the memory. Logic circuitry is coupled to the cache controller and the memory. The logic circuitry selectively separates the memory into multiple memory partitions. A first memory partition can be allocated to the computational circuitry and provide storage to the computational circuitry. A second memory partition can be allocated to the cache controller and provide storage to multiple components.Type: ApplicationFiled: August 19, 2020Publication date: September 22, 2022Applicant: Google LLCInventors: Suyog Gupta, Ravi Narayanaswami, Uday Kumar Dasari, Ali Iranli, Pavan Thirunagari, Vinu Vijay Kumar, Sunitha R. Kosireddy
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Publication number: 20210326683Abstract: Methods, systems, and apparatus, including computer-readable media, are described for a hardware circuit configured to implement a neural network. The circuit includes multiple super tiles. Each super tile includes a unified memory for storing inputs to a neural network layer and weights for the layer. Each super tile includes multiple compute tiles. Each compute tile executes a compute thread that is used to perform the computations to generate an output for the neural network layer. Each super tile includes arbitration logic coupled to the unified memory and each compute tile. The arbitration logic is configured to: pass inputs stored in the unified memory to the compute tiles; pass weights stored in the unified memory to the compute tiles; and pass, to the unified memory, the output generated for the layer based on computations performed at the compute tiles using the inputs and the weights for the layer.Type: ApplicationFiled: December 19, 2019Publication date: October 21, 2021Inventors: Ravi Narayanaswami, Dong Hyuk Woo, Suyog Gupta, Uday Kumar Dasari
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Patent number: 10540583Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.Type: GrantFiled: November 30, 2015Date of Patent: January 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Suyog Gupta
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Patent number: 10416965Abstract: A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET (metal oxide semiconductor field effect transistor) device and a gate voltage Vg of the MOSFET device so that the MOSFET device comprises a noise source configured in a manner such as to tune as desired a random number statistical distribution of an output of the MOSFET device. An output voltage of the MOSFET is provided as an input signal into a low noise amplifier and an output voltage of the low noise amplifier provides values for a random number generator.Type: GrantFiled: July 18, 2018Date of Patent: September 17, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chia-yu Chen, Damon Farmer, Suyog Gupta, Shu-jen Han
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Patent number: 10380479Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.Type: GrantFiled: October 8, 2015Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Suyog Gupta
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Patent number: 10338931Abstract: Techniques facilitating synchronization of processing engines for parallel deep learning are provided. In one example, a first processing component associated with a processor and processing components can: generate first output data based on input data associated with a machine learning process, wherein the processing components are communicatively coupled with an assignment component via a network; transmit the first output data to a second processing component of the processing components, wherein the first processing component and the second processing component comprise a first group of the processing components and the first group of the processing components is determined by the assignment component based on a first defined criterion; receive communication data generated by the second processing component; and generate second output data based on the communication data, wherein the second output data is an updated version of the first output data stored in the memory of the first processing component.Type: GrantFiled: April 29, 2016Date of Patent: July 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Suyog Gupta, Ravi Nair
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Publication number: 20190164050Abstract: A system, having a memory that stores computer executable components, and a processor that executes the computer executable components, reduces data size in connection with training a neural network by exploiting spatial locality to weight matrices and effecting frequency transformation and compression. A receiving component receives neural network data in the form of a compressed frequency-domain weight matrix. A segmentation component segments the initial weight matrix into original sub-components, wherein respective original sub-components have spatial weights. A sampling component applies a generalized weight distribution to the respective original sub-components to generate respective normalized sub-components. A transform component applies a transform to the respective normalized sub-components.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Inventors: Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Suyog Gupta, Pritish Narayanan
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Publication number: 20180341462Abstract: A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET (metal oxide semiconductor field effect transistor) device and a gate voltage Vg of the MOSFET device so that the MOSFET device comprises a noise source configured in a manner such as to tune as desired a random number statistical distribution of an output of the MOSFET device. An output voltage of the MOSFET is provided as an input signal into a low noise amplifier and an output voltage of the low noise amplifier provides values for a random number generator.Type: ApplicationFiled: July 18, 2018Publication date: November 29, 2018Inventors: Chia-yu Chen, Damon Farmer, Suyog Gupta, Shu-jen Han
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Patent number: 10095476Abstract: A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET device to maximize a transconductance of the MOSFET device and setting a gate voltage Vg of the MOSFET device to tune as desired a random number statistical distribution of an output of the MOSFET device. The MOSFET device includes a gate structure with an oxide layer including at least one artificial trapping layer in which carrier traps are designed to occupy a predetermined distance from conduction and valance bands of material of the artificial trapping layer.Type: GrantFiled: December 2, 2015Date of Patent: October 9, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chia-yu Chen, Damon Farmer, Suyog Gupta, Shu-jen Han
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Patent number: 10078496Abstract: An apparatus is presented for generating a true random number generator (TRNG). The apparatus includes a magnetic tunnel junction (MTJ) device including a first layer, a second layer, and third layer, as well as a bias circuit to bias the MTJ device along with a pulse height discriminator and a time-to-amplitude convertor to generate random bit-streams. The second layer is a barrier layer with an energy barrier height in the order of 20 kT, where k is the Boltzmann constant and T is the absolute temperature. Random flipping of an orientation of magnetization of the third layer is induced by thermal fluctuations in the MTJ device.Type: GrantFiled: February 23, 2017Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: Suyog Gupta, Chandrasekharan Kothandaraman, Jonathan Z. Sun
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Publication number: 20180239590Abstract: An apparatus is presented for generating a true random number generator (TRNG). The apparatus includes a magnetic tunnel junction (MTJ) device including a first layer, a second layer, and third layer, as well as a bias circuit to bias the MTJ device along with a pulse height discriminator and a time-to-amplitude convertor to generate random bit-streams. The second layer is a barrier layer with an energy barrier height in the order of 20kT, where k is the Boltzmann constant and T is the absolute temperature. Random flipping of an orientation of magnetization of the third layer is induced by thermal fluctuations in the MTJ device.Type: ApplicationFiled: February 23, 2017Publication date: August 23, 2018Inventors: Suyog Gupta, Chandrasekharan Kothandaraman, Jonathan Z. Sun
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Patent number: 10043875Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.Type: GrantFiled: January 5, 2018Date of Patent: August 7, 2018Assignee: International Business Machines CorporationInventors: Suyog Gupta, Bahman Hekmatshoartabari
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Patent number: 10038067Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.Type: GrantFiled: January 5, 2018Date of Patent: July 31, 2018Assignee: International Business Machines CorporationInventors: Suyog Gupta, Bahman Hekmatshoartabari
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Publication number: 20180145141Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.Type: ApplicationFiled: January 5, 2018Publication date: May 24, 2018Inventors: Suyog Gupta, Bahman Hekmatshoartabari
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Publication number: 20180130892Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Inventors: Suyog Gupta, Bahman Hekmatshoartabari
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Patent number: 9899485Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.Type: GrantFiled: June 7, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Suyog Gupta, Bahman Hekmatshoartabari
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Publication number: 20170351530Abstract: Techniques facilitating synchronization of processing engines for parallel deep learning are provided. In one example, a first processing component associated with a processor and processing components can: generate first output data based on input data associated with a machine learning process, wherein the processing components are communicatively coupled with an assignment component via a network; transmit the first output data to a second processing component of the processing components, wherein the first processing component and the second processing component comprise a first group of the processing components and the first group of the processing components is determined by the assignment component based on a first defined criterion; receive communication data generated by the second processing component; and generate second output data based on the communication data, wherein the second output data is an updated version of the first output data stored in the memory of the first processing component.Type: ApplicationFiled: April 29, 2016Publication date: December 7, 2017Inventors: Suyog Gupta, Ravi Nair
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Publication number: 20170352734Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventors: Suyog Gupta, Bahman Hekmatshoartabari