Patents by Inventor Suzanne Monsees

Suzanne Monsees has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a trench structure in a semiconductor substrate
    Patent number: 6107158
    Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: August 22, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Jie Zheng, Calvin Todd Gabriel, Suzanne Monsees
  • Sidewall profile
    Patent number: 5939765
    Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: August 17, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Jie Zheng, Calvin Todd Gabriel, Suzanne Monsees
  • Trench isolation method
    Patent number: 5882982
    Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: March 16, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Jie Zheng, Calvin Todd Gabriel, Suzanne Monsees