Abstract: The invention provides an electronic circuit apparatus having a plurality of electronic circuit units (101a-101n), a circuit board (102) and a connection unit (103), the circuit board (102) having a basic board element (200) and a plurality of additional board elements (201-204), the plurality of additional board elements (201-204) being connected to the basic board element (200) by means of connecting elements (301-304) and the circuit units being arranged on the additional board elements (201-204) in such a way that in each case identical signal propagation times are provided between the circuit units arranged on an additional board (201-204) and the connection unit (103).

Abstract: An integrated memory includes command terminals for receiving command signals in a normal operation and in a test operation of the memory, and also a signal terminal for receiving a further signal, which differs from the command signals. Registers store data patterns or data topologies for use in the test operation of the memory. A register decoder circuit serves for the selection of the registers, it being possible for inputs of the register decoder circuit to be connected to the command terminals and to the signal terminal for the purpose of selection of the registers in the test operation. The invention makes it possible, for the test operation, to address an increased number of registers without driving an additional external terminal pin. A method for testing the memory is also provided.

Abstract: A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier. Binary data signals read out from the memory cell are amplified and evaluated. The binary data signals can also be written back to the corresponding memory cell. Furthermore, an output unit for outputting the amplified and evaluated binary data signals and a coupling device between the memory cell array and the sense amplifier are provided. The coupling device has a preamplifier unit for preamplifying the data signals read out and a bridging unit for bridging the preamplifier unit in order to provide a writing back of the binary data signals to the memory cell of the memory cell array.

Abstract: A test-device for testing an electric circuit comprises a data stream generator for generating a first data stream to be fed to an electric circuit which generates a second data stream in response to the first data stream and a comparison-device for comparing two data streams. The test-device comprises further a self-test device configured to generate a third data stream used to test the comparison-device. The test-device is further configured to operate in a first operation mode and in a second operation mode. The comparison-device is configured to compare the first data stream with the second data stream during the first operation mode and is configured to compare the first data stream with the third data stream during the second operation mode.

Abstract: The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a select signal (103), and a connecting line (106) for connecting each electronic circuit unit (101a-101n) to the select signal generating unit (105), each of the electronic circuit units (101a-101n) of the electronic circuit module (100) furthermore in each case having a decoder unit (107a-107n) for decoding a predetermined bit sequence (108) of the select signal (103), at least one electronic circuit unit (101a-101n) being selectively selected by means of the predetermined bit sequence (108) of the select signal (103).

Abstract: A memory device for data storage has a memory module with at least one memory bank in which data are stored and from which the stored data are read out, and a logic unit for controlling a writing and a reading of data to and from the at least one memory bank. Furthermore, a test module for testing the functionality of the memory module is provided.

Abstract: Electronic memory apparatus, and method for deactivating redundant bit lines or word lines An electronic memory apparatus (100) having a memory cell array (101), a column address decoding unit (102) for decoding a column addressing signal (105) and for actuating an addressed bit line in the memory cell array (101), a column redundancy activation unit (103) for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus (100), a row address decoding unit (202) for decoding a row addressing signal (205) and for actuating an addressed word line in the memory cell array (101), and a row redundancy activation unit (203) for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus (100).

Abstract: The invention relates to a method for verification of electronic circuit units (101) which are contained in a circuit apparatus (100) with the operating state of the electronic circuit unit (101) to be verified being read by means of the circuit apparatus (100), an identification key (102, HWID) being read from the electronic circuit unit (101) to be verified, a reference identification key (105) being transmitted (S5) to the circuit apparatus (100), the identification key (102) being compared (S6) with the reference identification key (105), and a message for a user being emitted (S6) when the identification key (102) read from the electronic circuit unit (101) to be verified does not match the transmitted reference identification key (105).

Abstract: A testing method involves information being written to memory addresses and being read from the memory addresses. The method which logically combines parallel memory bank actuation of the memory addresses using an interleaved mode, which is implemented in relation to disjunct subareas of the memory banks, with one another. This shortens the test time required for testing the semiconductor memory.

Abstract: The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a select signal (103), and a connecting line (106) for connecting each electronic circuit unit (101a-101n) to the select signal generating unit (105), each of the electronic circuit units (101a-101n) of the electronic circuit module (100) furthermore in each case having a decoder unit (107a-107n) for decoding a predetermined bit sequence (108) of the select signal (103), at least one electronic circuit unit (101a-101n) being selectively selected by means of the predetermined bit sequence (108) of the select signal (103).

Abstract: The invention provides an electronic memory apparatus having a memory module which is arranged on a first circuit chip and which has at least one memory bank for electronically storing data, and having a test module which has analysis units for testing the memory module. In this arrangement, the memory module is arranged on a first circuit chip. The test module is arranged on a second circuit chip which is provided so as to be physically separate from the memory module arranged on the first circuit chip, with the test module being connected to the memory module via a communication device.

Abstract: A test-device for testing an electric circuit comprises a data stream generator for generating a first data stream to be fed to an electric circuit which generates a second data stream in response to the first data stream and a comparison-device for comparing two data streams. The test-device comprises further a self-test device configured to generate a third data stream used to test the comparison-device. The test-device is further configured to operate in a first operation mode and in a second operation mode. The comparison-device is configured to compare the first data stream with the second data stream during the first operation mode and is configured to compare the first data stream with the third data stream during the second operation mode.

Abstract: The invention provides a memory device for data storage having a memory module (100) having at least one memory bank (101a-101n) in which data to be stored are stored and from which the stored data are read out, and a logic unit (106) for controlling a writing and a reading of data to and from the at least one memory bank (101a-101n), and a test module (200) for testing the functionality of the memory module (100). The test module (200) is arranged in a manner separated from the memory module (100) in a separate circuit unit, and is connected to the memory module (100) via a communication device (204) for the exchange of communication signals (206a-206d; 207).

Abstract: The invention provides a test apparatus for testing an electronic circuit unit to be tested. The test apparatus comprises a read-only memory for buffer-storing a test data stream read from the circuit unit to be tested in a manner dependent on a clock signal. The test apparatus further comprises a multiplexing unit for alternately outputting even data and odd data of the test data stream, and a driver device for driving the read-out test data stream to an output unit. Provision is made for a comparison device for bit by bit comparison of the even data and the odd data with one another and a blocking device for blocking the driver device if the read-out even data and the read-out odd data of the test data stream do not match.

Abstract: The invention provides a memory device having a memory cell array (100) having at least one memory cell (101), at least one sense amplifier (105), by means of which binary data signals read out from the memory cell (101) are amplified and evaluated, and can also be written back to the corresponding memory cell, and an output unit for outputting the amplified and evaluated binary data signals, provision further being made of a coupling device (200) between the memory cell array (100) and the sense amplifier (105), which coupling device comprises a preamplifier unit (201) for preamplifying the data signals read out and a bridging unit (202) for bridging the preamplifier unit in order to provide a writing back of the binary data signals to the memory cell of the memory cell array.

Abstract: The invention provides a method for controlling circuit functions of an electronic circuit apparatus, at least one input command signal (201), which is input via an external command bus (205), being buffer-stored in an input buffer (203) of the electronic circuit apparatus, the given input command signal (201) being processed in a processing unit (204) of the electronic circuit apparatus in such a manner that it is possible to control circuit functions of the circuit apparatus, and, before the input command signal (201) is forwarded to the processing unit (204), the input command signal (201) being monitored using a command control device (100) which is connected between the input buffer (203) and the processing unit (204). The invention also relates to an electronic circuit apparatus for carrying out the command monitoring method.

Abstract: The invention provides an electronic circuit apparatus having a plurality of electronic circuit units (101a-101n), a circuit board (102) and a connection unit (103), the circuit board (102) having a basic board element (200) and a plurality of additional board elements (201-204), the plurality of additional board elements (201-204) being connected to the basic board element (200) by means of connecting elements (301-304) and the circuit units being arranged on the additional board elements (201-204) in such a way that in each case identical signal propagation times are provided between the circuit units arranged on an additional board (201-204) and the connection unit (103).

Abstract: The invention provides a test apparatus for testing an electronic circuit device (101) to be tested by means of a test system (100), having an interface unit (102) for connecting the circuit device (101) to be tested to the test system (100), an address decoding unit (107) for decoding external addressing data (104) input by means of the test system (100) into internal addressing data (110, 112) and for addressing memory cells of a memory cell array (108) of the circuit device (101) to be tested with the internal addressing data (110, 112), and a memory data converter (115) for converting logical memory data (106), which are fed by the test system (100), into physical memory data (114). The memory data converter (115) carries out a conversion of the logical memory data (106) fed by the test system (100) into physical memory data (114) in a manner dependent on the internal addressing data (110, 112) of the circuit device (101) to be tested.

Abstract: Electronic memory apparatus, and method for deactivating redundant bit lines or word lines The invention provides an electronic memory apparatus (100) having a memory cell array (101), a column address decoding unit (102) for decoding a column addressing signal (105) and for actuating an addressed bit line in the memory cell array (101), a column redundancy activation unit (103) for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus (100), a row address decoding unit (202) for decoding a row addressing signal (205) and for actuating an addressed word line in the memory cell array (101), and a row redundancy activation unit (203) for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus (100).

Abstract: One embodiment of the invention provides a RAM memory circuit having k?2 banks, each of which having a multiplicity of memory cells and a selection device to simultaneously select groups of in each case n?2 memory cells of the bank for the writing or reading of n parallel data. For the fast testing of all the banks, devices are included for the parallel switching of the banks such that reading and writing may be effected simultaneously at all the banks. For each bank, a dedicated evaluation device is included for comparing the n data respectively read out at the relevant bank with a reference information item, which is representative of the write data which have previously been written in at the currently selected memory cell group of the bank, and for providing a result information item, comprising 1?m?n/k bits, each of which indicates whether a subset precisely assigned to it from m subsets of the n read data corresponds to a part of the reference information item which is precisely assigned to said subset.