Abstract: A scannable limited switch dynamic logic (LSDL) circuit including a data input and a data output, a combinational logic circuit in communication with the data input, a pre-charge circuit in communication with the combinational logic circuit, a footer circuit in communication with the combinational logic, a keeper circuit in communication with the combinational logic circuit and the pre-charge circuit, a scan input connected to the data input, a scan input circuit in communication with the scan input, the combinational logic circuit, the pre-charge circuit, and the keeper circuit, a modified inverter circuit in communication with the combinational logic circuit, the pre-charge circuit, the keeper circuit, and the scan input circuit, a parallel gate circuit in communication with the modified inverter circuit, a series gate circuit in communication with the modified inverter circuit and the parallel gate circuit, a feedback inverter connected between an internal node and a feedback node, and an output buffer con