Abstract: A vertical cavity surface emitting laser (VCSEL) (100) has a substrate (104), on which are disposed first and second distributed Bragg reflectors (DBRs) (106, 112), each DBR comprising a stack of layers of alternating refractive index, an active layer (108) disposed between the DBRs, and an aperture layer (110) disposed either between the DBRs or within one of the DBRs. The aperture layer (110) has a border (116) having an internal boundary with a plurality of indented portions defining one or more apertures. Such a VCSEL is easily manufacturable and provides a narrow bandwidth output, as well as mitigating at least some of the problems of prior art VCSELs. Mesa (102) may be etched to be non-circular and subsequent selective oxidation of aperture layer (110) results in a non-circular current confinement aperture (114) promoting higher-order lateral modes (LP21).

Abstract: A vertical cavity surface emitting laser (VCSEL) (100) has a substrate (104), on which are disposed first and second distributed Bragg reflectors (DBRs) (106, 112), each DBR comprising a stack of layers of alternating refractive index, an active layer (108) disposed between the DBRs, and an aperture layer (110) disposed either between the DBRs or within one of the DBRs. The aperture layer (110) has a border (116) having an internal boundary with a plurality of indented portions defining one or more apertures. Such a VCSEL is easily manufacturable and provides a narrow bandwidth output, as well as mitigating at least some of the problems of prior art VCSELs. Mesa (102) may be etched to be non-circular and subsequent selective oxidation of aperture layer (110) results in a non-circular current confinement aperture (114) promoting higher-order lateral modes (LP21).

Abstract: A design of a vertical cavity surface emitting laser chip suitable for high speed data communication. An intracavity contact to the doped layers of the bottom mirror is formed so that both contacts are on the top epitaxial side of the wafer. These main structural features can be used to reduce the bond pad capacitance by a suitable spatial separation of metallizations of the p and n contact. The bond pads are processed as a short symmetric coplanar line in a ground signal ground configuration which allows flexible device testing and packaging. A significant capacitance between the pads of the center strip and the outer ground strips is avoided by etching the doped semiconductor layers between these strips down to the semi-insulating substrate. This design avoids pad metallizations and the corresponding critical photolithographic steps over large height differences from the vertical cavity surface emitting laser mesa top to the substrate.

Abstract: A design of a single vertical cavity surface emitting laser chip and a vertical cavity surface emitting laser array suitable for high speed data communication is presented. The vertical cavity surface emitting laser epitaxial layer structure is grown on semi-insulating substrate or includes an undoped layer sequence below the central vertical cavity surface emitting layer cavity. Additionally, an intracavity contact to the doped layers of the bottom mirror is formed so that both contacts are on the top epitaxial side of the wafer. These main structural features can be used to reduce the bond pad capacitance to very low values by a suitable spatial separation of metallizations of the p and n contact. With the vertical cavity surface emitting laser chip design described here, the bond pads are processed as a short symmetric coplanar line in a ground signal ground configuration which allows flexible device testing and packaging.