Patents by Inventor Sven Kalms
Sven Kalms has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8879260Abstract: The memory module comprises a circuit board with a first and a second side, wherein memory chips are arranged at least on the first side. A longitudinally extending module heat conductor is arranged on the first side. The module heat conductor comprises a contact surface configured to contact a heat transfer system.Type: GrantFiled: August 7, 2012Date of Patent: November 4, 2014Assignee: Qimonda AGInventors: Sven Kalms, Christian Weiss
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Publication number: 20120314363Abstract: The memory module comprises a circuit board with a first and a second side, wherein memory chips are arranged at least on the first side. A longitudinally extending module heat conductor is arranged on the first side. The module heat conductor comprises a contact surface configured to contact a heat transfer system.Type: ApplicationFiled: August 7, 2012Publication date: December 13, 2012Inventors: Sven Kalms, Christian Weiss
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Patent number: 8238101Abstract: The memory module comprises a circuit board with a first and a second side, wherein memory chips are arranged at least on the first side. A longitudinally extending module heat conductor is arranged on the first side. The module heat conductor comprises a contact surface configured to contact a heat transfer system.Type: GrantFiled: August 29, 2008Date of Patent: August 7, 2012Assignee: Qimonda AGInventors: Sven Kalms, Christian Weiss
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Patent number: 8094654Abstract: An electronic assembly includes electronic modules connected in a series circuit such that a particular number of input connections of one of the electronic modules is connected with the particular number of output connections of another of the electronic modules. Each electronic module is configured to pass on an information which each electronic module receives on an input side at an nth of each electronic module's input connections to an nth of each electronic module's output connections. The input connections and output connections of each electronic module are arranged in a same geometric arrangement.Type: GrantFiled: September 27, 2006Date of Patent: January 10, 2012Assignee: Qimonda AGInventors: Sven Kalms, Christian Weiss
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Patent number: 7519894Abstract: A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are connected to the memory controller via a common ECC channel. Each external ECC module is assigned to a group of the memory modules. The memory modules of one group with respective ECC modules are synchronously operated by the memory controller.Type: GrantFiled: June 14, 2005Date of Patent: April 14, 2009Assignee: Infineon Technologies AGInventors: Christian Weiβ, Sven Kalms, Hermann Ruckerbauer
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Publication number: 20090080151Abstract: The memory module comprises a circuit board with a first and a second side, wherein memory chips are arranged at least on the first side. A longitudinally extending module heat conductor is arranged on the first side. The module heat conductor comprises a contact surface configured to contact a heat transfer system.Type: ApplicationFiled: August 29, 2008Publication date: March 26, 2009Inventors: Sven Kalms, Christian Weiss
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Patent number: 7362650Abstract: Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.Type: GrantFiled: March 30, 2006Date of Patent: April 22, 2008Assignee: Infineon Technologies AGInventors: Helmut Kandolf, Sven Kalms, Maksim Kuzmenka, Michael Hausmann
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Publication number: 20070106837Abstract: An electronic assembly includes electronic modules connected in a series circuit such that a particular number of input connections of one of the electronic modules is connected with the particular number of output connections of another of the electronic modules. Each electronic module is configured to pass on an information which each electronic module receives on an input side at an nth of each electronic module's input connections to an nth of each electronic module's output connections. The input connections and output connections of each electronic module are arranged in a same geometric arrangement.Type: ApplicationFiled: September 27, 2006Publication date: May 10, 2007Inventors: Sven Kalms, Christian Weiss
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Patent number: 7191276Abstract: One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or commandType: GrantFiled: June 25, 2004Date of Patent: March 13, 2007Assignee: Infineon Technologies AGInventors: Sven Kalms, Helmut Kandolf
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Publication number: 20070011574Abstract: A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are connected to the memory controller via a common ECC channel. Each external ECC module is assigned to a group of the memory modules. The memory modules of one group with respective ECC modules are synchronously operated by the memory controller.Type: ApplicationFiled: June 14, 2005Publication date: January 11, 2007Inventors: Christian Weiss, Sven Kalms, Hermann Ruckerbauer
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Publication number: 20060250881Abstract: Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.Type: ApplicationFiled: March 30, 2006Publication date: November 9, 2006Inventors: Helmut Kandolf, Sven Kalms, Maksim Kuzmenka, Michael Hausmann
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Publication number: 20050027923Abstract: One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or commandType: ApplicationFiled: June 25, 2004Publication date: February 3, 2005Inventors: Sven Kalms, Helmut Kandolf