Abstract: An arrangement for ciphering and deciphering comprises a number of cycle length counters. Each of the counters has a different cycle length and generates a series of bits by scanning associated memory fields containing internal-key-information. The series of bits are combined in a logical unit in order to obtain a ciphered series. The arrangement includes a plurality of memories each comprising a number of memory fields corresponding to the number of counters. Switches are arranged to select internal-key-information by selecting memory fields from different memories depending on a control device, which is operated by certain character combinations in the transmitted text on the sender side and on the receiver side of the system.