Patents by Inventor Sven Trester

Sven Trester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769764
    Abstract: Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 26, 2023
    Assignee: NXP B.V.
    Inventor: Sven Trester
  • Patent number: 11177210
    Abstract: An integrated circuit includes functional structures and non-functional structures. The functional structures include one or more functional metal structures. The non-functional structures include one or more non-functional metal structures. At least one of the one or more non-functional metal structures is connected to at least one of the one or more functional metal structures. For example, the at least one non-functional metal structure is connected to the at least one functional metal structure through a via. Alternatively, the at least one non-functional metal structure is connected to the at least one functional metal structure by physically contacting the at least one functional metal structure without using a via.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP B.V.
    Inventors: Sven Trester, Tobias Richard Erich Nink
  • Publication number: 20210202379
    Abstract: An integrated circuit includes functional structures and non-functional structures. The functional structures include one or more functional metal structures. The non-functional structures include one or more non-functional metal structures. At least one of the one or more non-functional metal structures is connected to at least one of the one or more functional metal structures. For example, the at least one non-functional metal structure is connected to the at least one functional metal structure through a via. Alternatively, the at least one non-functional metal structure is connected to the at least one functional metal structure by physically contacting the at least one functional metal structure without using a via.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: Sven Trester, Tobias Richard Erich Nink
  • Publication number: 20210020623
    Abstract: Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 21, 2021
    Inventor: Sven TRESTER
  • Patent number: 10755019
    Abstract: In accordance with a first aspect of the present disclosure, a method of designing an integrated circuit is conceived, comprising: placing integrated circuit cells that include supply pins in a plurality of predefined rows; determining blocked areas for supply pin extensions; extending the supply pins outside said blocked areas. A corresponding integrated circuit is also provided.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 25, 2020
    Assignee: NXP B.V.
    Inventors: Sven Trester, Claus Dieter Grzyb
  • Publication number: 20190236235
    Abstract: In accordance with a first aspect of the present disclosure, a method of designing an integrated circuit is conceived, comprising: placing integrated circuit cells that include supply pins in a plurality of predefined rows; determining blocked areas for supply pin extensions; extending the supply pins outside said blocked areas. A corresponding integrated circuit is also provided.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 1, 2019
    Inventors: Sven Trester, Claus Dieter Grzyb
  • Patent number: 10115676
    Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate. The integrated circuit also includes a metallization stack located on a major surface of the semiconductor substrate. The metallization stack includes a plurality of metal layers including patterned metal features. Each metal layer of the metallization stack is separated by an intervening dielectric layer. The metallization stack forms a first grid including patterned metal features for supplying power and signal connections to components of the integrated circuit located in the semiconductor substrate. The metallization stack also forms a second grid for securing the integrated circuit against electromagnetic attacks. The second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack. The patterned metal features of the second grid are electrically connected to the first grid.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 30, 2018
    Assignee: NXP B.V.
    Inventor: Sven Trester
  • Patent number: 9892966
    Abstract: A method of designing a layout of a metallization stack of an integrated circuit (IC), where the stack includes metal layers having patterned metal features. The method includes determining a layout of a first grid of the metallization stack, including patterned metal features for supplying power and providing signal connections to components of the IC. The method also includes determining a layout of a second grid of the stack for securing the IC against electromagnetic attacks. The second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack. The patterned metal features of the second grid are electrically connected to the first grid. The method further includes determining at least one layout change for the metallization stack in accordance with an engineering change order.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: February 13, 2018
    Assignee: NXP B.V.
    Inventor: Sven Trester
  • Patent number: 9741671
    Abstract: A semiconductor die with backside protection includes an active region and a first polysilicon layer formed on a front side of a semiconductor substrate. A signal net is connected to the first polysilicon layer by way of a metal contact and a conductive wire is formed above the active region. During an invasive attack, when a trench is formed in the substrate and an electrically conductive filling is deposited in the trench, the signal net, the conductive wire, and the first polysilicon shape form a short-circuit, which renders the die dysfunctional and thereby foiling the invasive attack.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 22, 2017
    Assignee: NXP B.V.
    Inventors: Sven Trester, Claus Grzyb
  • Publication number: 20170125357
    Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate. The integrated circuit also includes a metallisation stack located on a major surface of the semiconductor substrate. The metallisation stack includes a plurality of metal layers including patterned metal features. Each metal layer of the metallisation stack is separated by an intervening dielectric layer. The metallisation stack forms a first grid including patterned metal features for supplying power and signal connections to components of the integrated circuit located in the semiconductor substrate. The metallisation stack also forms a second grid for securing the integrated circuit against electromagnetic attacks. The second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallisation stack. The patterned metal features of the second grid are electrically connected to the first grid.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 4, 2017
    Inventor: Sven Trester