Abstract: The system contains at least one basic block formed by a first multiplexer having an output is connected to a flag register memory, implemented as a LUT table. An output of a circuit for write permit to the memory is connected to the input of the write signal to the memory, which is further equipped with the clock signal input and the data input. The data output from the memory of each basic block is connected to a masking block relevant for the given basic block. The outputs of these masking blocks are connected to the inputs of the second multiplexer, while its output is the output of the system of flags. The input of the control signal for writing to the memory of each basic block is connected to the output of the demultiplexer and to the second input of the masking block for the given basic block.

Abstract: The system contains at least one basic block formed by a first multiplexer having an output is connected to a flag register memory, implemented as a LUT table. An output of a circuit for write permit to the memory is connected to the input of the write signal to the memory, which is further equipped with the clock signal input and the data input. The data output from the memory of each basic block is connected to a masking block relevant for the given basic block. The outputs of these masking blocks are connected to the inputs of the second multiplexer, while its output is the output of the system of flags. The input of the control signal for writing to the memory of each basic block is connected to the output of the demultiplexer and to the second input of the masking block for the given basic block.

Abstract: The presented invention enables the reception of video signals with variable channel synchronization. All logic elements are located on the receiver side that can work with any transmitter. The receiver comprises one or more sets of modules for image processing. These sets of modules adapt the speed of sending data to the frame generator to the speed of data creation on the transmitter side without the use of a precise time pulse source on both sides of the transfer and without feedback from the receiver to the transmitter. The receiver further includes a memory of channel synchronization configuration which determines the allocation of synchronized channels to groups and the detector of starts of frames. These, along with multiplexers of clock signals, ensure the synchronization of channels within groups and allows for modifying this channel distribution.

Abstract: The presented invention enables the reception of video signals with variable channel synchronization. All logic elements are located on the receiver side that can work with any transmitter. The receiver comprises one or more sets of modules for image processing. These sets of modules adapt the speed of sending data to the frame generator to the speed of data creation on the transmitter side without the use of a precise time pulse source on both sides of the transfer and without feedback from the receiver to the transmitter. The receiver further includes a memory of channel synchronization configuration which determines the allocation of synchronized channels to groups and the detector of starts of frames. These, along with multiplexers of clock signals, ensure the synchronization of channels within groups and allows for modifying this channel distribution.

Abstract: A device based on the proposed solution allows high-definition video transmissions with low latency over an asynchronous packet computer network such as Ethernet. The transmitter and receiver comprise a video input or output module, an FPGA board, and an optical transceiver for transmission and reception of a signal over the Ethernet network. The principle of the new device is that the receiver comprises one or more tunable oscillators connected to the FPGA board comprising a module for packet reception, and one or more sets of modules for video data processing.

Abstract: A device based on the proposed solution allows high-definition video transmissions with low latency over an asynchronous packet computer network such as Ethernet. The transmitter and receiver comprise a video input or output module, an FPGA board, and an optical transceiver for transmission and reception of a signal over the Ethernet network. The principle of the new device is that the receiver comprises one or more tunable oscillators connected to the FPGA board comprising a module for packet reception, and one or more sets of modules for video data processing.