Abstract: An electrostatic discharge (ESD) protection device including a stack of ESD clamps, a trigger circuit, and a transistor. The trigger circuit may respond to an ESD event by conducting current, which may cause the transistor to turn on. A combination of the trigger circuit conducting current and the transistor turning on may trigger the ESD clamps into a conducting state to shunt current from a first node to a second node.

Abstract: An electrostatic discharge (ESD) protection device including a stack of ESD clamps, a trigger circuit, and a transistor. The trigger circuit may respond to an ESD event by conducting current, which may cause the transistor to turn on. A combination of the trigger circuit conducting current and the transistor turning on may trigger the ESD clamps into a conducting state to shunt current from a first node to a second node.

Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.

Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.

Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.

Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed including at least a clamping device, a switching device, and a voltage limiter. The ESD protection circuit may include devices of different voltage domains. The switching device may be in series with the clamping device to block at least a portion of a voltage from dropping across the clamping device. The switching device may sustain higher maximum operating voltages than the clamping device.

Abstract: An improved ESD protection circuit having an ESD device and a triggering device to provide a continuously adjustable trigger voltage. This can be accomplished by various techniques such as placing a selected number of triggering elements in series, modifying the gate control circuitry and varying the size of the triggering elements.

Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.

Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection circuit is configured to operate in high voltage domains. The ESD protection device may further include stacked NMOS or PMOS devices. The gates of the MOS devices may be driven by respective inverters. The inverters may be coupled to a voltage divider and may be triggered by respective trigger circuits. Power nodes of the inverters may be connected such that devices in the ESD protection circuit are exposed to voltages that are within their maximum voltage rating.

Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.

Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.

Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection circuit is configured to operate in high voltage domains. The ESD protection device may further include stacked NMOS or PMOS devices. The gates of the MOS devices may be driven by respective inverters. The inverters may be coupled to a voltage divider and may be triggered by respective trigger circuits. Power nodes of the inverters may be connected such that devices in the ESD protection circuit are exposed to voltages that are within their maximum voltage rating.

Abstract: An ESD protection circuit including an SCR having at least one PNP transistor and at least one NPN transistor such that at least one of the PNP transistor and the NPN transistor having an additional second collector. The circuit further including at least one control circuit coupled to the at least one second collector to control holding voltage of the SCR.

Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.