Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

Abstract: A processor is provided configured to traverse rays through a BVH tree; record trails of successful ray-primitive intersections from hit primitives to a root node of the BVH tree; update node visit counters, wherein the node visit counters correspond to the number of times a child node was taken on the path to the root node, based on the recorded trails; determine a traversal order for child nodes of a current node based on the node visit counters; and traverse the child nodes according to the determined traversal order.

Abstract: A processor receives neural network weights and programs a lookup table based on those weights to process neural network operations. The lookup table transforms input values with a smaller bit count to output values with a larger bit count, allowing flexible distribution of accuracy. For example, 4-bit inputs can be translated to 8-bit outputs using a 16-entry lookup table. The lookup table can also replace mathematical operations like multiplication and addition. A 4-bit by 4-bit multiplication can be implemented with a 256-entry lookup table having 8 or more output bits, providing flexibility in numeric formats. This approach enables efficient processing of neural networks with programmable lookup tables that transform small bit count weights to larger internal representations.

Abstract: A processor executes instructions for dynamic construction of opacity micro-maps (OMMs) in runtime. The processor initializes OMM bits to indicate ambiguous opacity, executes a shader when a triangle is first intersected, determines sub-triangle opacity based on shader execution, updates the OMM with opacity information, and uses the updated OMM for subsequent ray intersections. Two modes are supported: explicit mode using an API for application-defined opacity decisions, and implicit mode for compiler-based opacity analysis. The processor may cache shader results, select subdivision levels based on triangle size, and suppress or trigger shader invocations for subsequent intersections. This approach enables efficient, dynamic OMM generation and improves ray tracing performance.

Abstract: A processor for raytracing is provided, the processor being configured to: generate a bounding volume hierarchy, quantize at least one bounding box associated with the bounding volume hierarchy, dynamically allocate a number of quantization bits for at least one of x, y, and z dimensions of the at least one bounding box, wherein a variable number of quantization bits per dimension is used in the quantization.

Abstract: A processor for ray tracing is provided. The processor is configured to provide an acceleration structure including at least one junction node, obtain rays with associated detail base and detail attenuation parameters, and traverse the acceleration structure using the generated rays, wherein the junction node comprises: a junction factor, a pointer to a low level of detail acceleration structure, and a pointer to a high level of detail acceleration structure. The processor is configured to determine a junction entrance value based on the detail base parameter, the detail attenuation parameter, and a distance value, and to compare the junction entrance value to the junction factor to determine which level of detail acceleration structure to traverse.

Abstract: A processor performs matrix multiplication operations using low bit fixed point formats. The processor encodes matrix weights to 1-bit or 2-bit formats, performs matrix multiplications using the encoded weights, and accumulates results. Supported formats include symmetric binary (1-bit, ?1/+1), asymmetric binary (1-bit, 0/+1), ternary (2-bit, ?1/0/+1), and quaternary (2-bit, ?2/?1/+1/+2). Multiplication uses XNOR, AND, or 2-bit multiplier operations. Accumulation uses higher precision, with results rounded to the low-bit format. This enables efficient neural network inference with 2-4× performance gain over 4-bit formats.

Abstract: A processor is provided to perform a raytracing process, wherein the raytracing process includes: determining a bounding volume hierarchy (BVH) structure with leaf nodes; storing a plurality of triangles as meshlets in leaf nodes; obtaining a ray tracing acceleration data structure (RTAS) comprising BVH leaf nodes and triangles; transforming vertices of the triangles into a unit ray coordinate space; perform a culling procedure on the transformed triangles; and intersect remaining triangles with a ray in the unit ray space.

Abstract: A graphics processing system and method for ray tracing traversal in a hierarchical acceleration structure utilizes a memory and processor. The processor evaluates nodes and ray intersections with child node bounding volumes, marks nodes for reevaluation, and stores thresholds related to child node intersections. The system returns to marked nodes when current node intersections exceed thresholds. Nodes are marked using one bit in the internal structure and stored as stack offsets. Thresholds are calculated using near and far intersection points. Child nodes exceeding thresholds are placed on a stack before returning to marked nodes. This approach enables efficient traversal path selection, reducing unnecessary checks and improving ray tracing performance in complex scenes.

Abstract: A computing system and method generate bounding boxes for objects in a three-dimensional scene. A grid generator creates a 3D grid, and a histogram generator builds a histogram of primitive intersections with grid cells. A neural network receives the histogram as input and generates bounding boxes around objects. A box optimizer minimizes the sum of surface areas of the bounding boxes. The histogram can be compressed, using a single bit per bin to indicate primitive presence. Primitives are assigned to child nodes based on proximity or fit. The system provides efficient and optimized bounding box generation for computer graphics applications.

Abstract: Apparatus and method for a biased BVH traversal path. For example, one embodiment of an apparatus comprises: ray tracing traversal hardware logic to traverse a ray through nodes of a bounding volume hierarchy (BVH); and stack management hardware logic to push and pop entries on a traversal stack, each entry corresponding to a node of the BVH, wherein the ray tracing traversal hardware logic is to determine an order in which to push entries to the traversal stack based on both a first intersection value corresponding to a closest intersection point between the ray and a BVH node and a farthest intersection value between the ray and the BVH node. In addition, the ray traversal hardware logic may determine the order in which to push the entries to the traversal stack further based on a probability density value corresponding to a probability of a ray hitting geometry inside of the BVH.

Abstract: Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.

Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

Abstract: Apparatus and method for lossy displaced mesh compression. For example, one embodiment of an apparatus comprises: displacement mapping circuitry/logic to generate an original displacement-mapped mesh by performing a displacement mapping of a plurality of vertices of a base subdivision mesh; and mesh compression circuitry/logic to compress the original displacement-mapped mesh, the mesh compression circuitry/logic comprising a quantizer to quantize the displacement mapping of the plurality of vertices in view of a base mesh to generate a displacement array.

Abstract: Apparatus and method for camera-aware BVH re-braiding. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH); and BVH processing hardware logic to modify the BVH to reduce spatial overlap between one or more BVH subtrees based on a detected camera position to produce a modified BVH.

Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

Abstract: Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.

Abstract: Apparatus and method for extended cache control operations for scratch space usage. For example, one embodiment of an apparatus comprises: a cache subsystem comprising at least a first level (L1) cache; a graphics processor core block to execute a workload using a temporary scratch memory space containing cacheable data, resulting in partially dirty cache lines in the cache subsystem containing data which is no longer needed, the graphics processor core block to execute a cache control instruction including fields to identify one or more of the partially dirty cache lines associated with the workload, the cache control instruction executed to reduce one or more instances of unnecessary memory read and memory write operations.

Abstract: Apparatus and method for throttling ray tracing operations based on a cache hit rate. For example, one embodiment of a processor comprises: a cache subsystem comprising one or more caches; circuitry to track a plurality of hits and misses in the cache subsystem for data accesses associated with ray tracing operations; and thread management logic to dynamically control a working set size for the ray tracing operations based on the plurality of hits and misses.