Patents by Inventor Sw Wang

Sw Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006363
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
    Type: Application
    Filed: September 13, 2023
    Publication date: January 4, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
  • Patent number: 11791297
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: October 17, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sw Wang, Ch Chew, Eiji Kurose, How Kiat Liew
  • Publication number: 20220157756
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 19, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
  • Patent number: 11244918
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: February 8, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sw Wang, CH Chew, Eiji Kurose, How Kiat Liew
  • Patent number: 10699989
    Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Sw Wang, Kai Chat Tan
  • Patent number: 10319639
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: June 11, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan
  • Publication number: 20190122963
    Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.
    Type: Application
    Filed: July 10, 2018
    Publication date: April 25, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol PRAJUCKAMOL, Sw WANG, Kai Chat TAN
  • Publication number: 20190057947
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
  • Publication number: 20190057900
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh KRISHNAN, Sw WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
  • Patent number: 10056317
    Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 21, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Sw Wang, Kai Chat Tan