Patents by Inventor Sw Wang
Sw Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006363Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: September 13, 2023Publication date: January 4, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Patent number: 11791297Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: GrantFiled: February 4, 2022Date of Patent: October 17, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw Wang, Ch Chew, Eiji Kurose, How Kiat Liew
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Publication number: 20220157756Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: February 4, 2022Publication date: May 19, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Patent number: 11244918Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: GrantFiled: August 17, 2017Date of Patent: February 8, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw Wang, CH Chew, Eiji Kurose, How Kiat Liew
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Patent number: 10699989Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.Type: GrantFiled: July 10, 2018Date of Patent: June 30, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Sw Wang, Kai Chat Tan
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Patent number: 10319639Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: August 17, 2017Date of Patent: June 11, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20190122963Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.Type: ApplicationFiled: July 10, 2018Publication date: April 25, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Sw WANG, Kai Chat TAN
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Publication number: 20190057947Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Publication number: 20190057900Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Patent number: 10056317Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.Type: GrantFiled: October 20, 2017Date of Patent: August 21, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Sw Wang, Kai Chat Tan