Patents by Inventor Swami Venkataraman

Swami Venkataraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiprocessor node controller circuit and method
    Patent number: 7406086
    Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: July 29, 2008
    Assignee: Silicon Graphics, Inc.
    Inventors: Martin M. Deneroff, Givargis G. Kaldani, Yuval Koren, David Edward McCracken, Swami Venkataraman
  • Multiprocessor node controller circuit and method
    Patent number: 6751698
    Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: June 15, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Martin M. Deneroff, Givargis G. Kaldani, Yuval Koren, David Edward McCracken, Swami Venkataraman