Patents by Inventor Swaminathan Sivakumar

Swaminathan Sivakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210151438
    Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: November 20, 2019
    Publication date: May 20, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
  • Publication number: 20210125866
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventors: Oleg GOLONZKA, Swaminathan SIVAKUMAR, Charles H. WALLACE, Tahir GHANI
  • Publication number: 20210082800
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 18, 2021
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 10910265
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Oleg Golonzka, Swaminathan Sivakumar, Charles H. Wallace, Tahir Ghani
  • Patent number: 10892223
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Publication number: 20200388689
    Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.
    Type: Application
    Filed: February 23, 2018
    Publication date: December 10, 2020
    Inventors: Leonard P. GULER, Biswajeet GUHA, Mark ARMSTRONG, William HSU, Tahir GHANI, Swaminathan SIVAKUMAR
  • Publication number: 20200388534
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 10, 2020
    Inventors: Leonard P. GULER, Michael HARPER, Suzanne S. RICH, Charles H. WALLACE, Curtis WARD, Richard E. SCHENKER, Paul NYHUS, Mohit K. HARAN, Reken PATEL, Swaminathan SIVAKUMAR
  • Publication number: 20200219978
    Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Leonard P. GULER, Biswajeet GUHA, Tahir GHANI, Swaminathan SIVAKUMAR
  • Publication number: 20200220016
    Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.
    Type: Application
    Filed: January 4, 2019
    Publication date: July 9, 2020
    Inventors: Leonard GULER, Nick LINDERT, Biswajeet GUHA, Swaminathan SIVAKUMAR, Tahir GHANI
  • Publication number: 20200211970
    Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Wilfred GOMES, Mark BOHR, Rajabali KODURI, Leonard NEIBERG, Altug KOKER, Swaminathan SIVAKUMAR
  • Publication number: 20200194309
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventors: Oleg GOLONZKA, Swaminathan SIVAKUMAR, Charles H. WALLACE, Tahir GHANI
  • Patent number: 10607884
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Oleg Golonzka, Swaminathan Sivakumar, Charles H. Wallace, Tahir Ghani
  • Publication number: 20200098878
    Abstract: Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Leonard P. GULER, Biswajeet GUHA, Tahir GHANI, Swaminathan SIVAKUMAR
  • Patent number: 10600678
    Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Elliot N. Tan, Paul A. Nyhus, Swaminathan Sivakumar
  • Publication number: 20200091144
    Abstract: Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Leonard P. GULER, Biswajeet GUHA, Tahir GHANI, Swaminathan SIVAKUMAR
  • Publication number: 20200091101
    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Applicant: INTEL CORPORATION
    Inventors: CHARLES H. WALLACE, HOSSAM A. ABDALLAH, ELLIOT N. TAN, SWAMINATHAN SIVAKUMAR, OLEG GOLONZKA, ROBERT M. BIGWOOD
  • Publication number: 20200066629
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: December 23, 2016
    Publication date: February 27, 2020
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 10490519
    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Charles H. Wallace, Hossam A. Abdallah, Elliot N. Tan, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood
  • Patent number: 10459338
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Eungnak Han, Swaminathan Sivakumar, Ernisse S. Putna
  • Patent number: 10409152
    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Charles H. Wallace, Hossam A. Abdallah, Elliot N. Tan, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood