Patents by Inventor Swaminathan Venkateasan

Swaminathan Venkateasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for generating post-silicon validation tests
    Patent number: 9823305
    Abstract: A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 21, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Meir Ovadia, Swaminathan Venkateasan