Abstract: A system for predictive analysis and/or process control, preferably including one or more communication and/or computing systems, and optionally including one or more entities and/or sensors. A method for predictive analysis and/or machine operation, preferably including receiving entity data and determining one or more latent features, and optionally including determining one or more response reconstructions, determining a processed representation of the entity data, determining entity information, and/or acting based on entity information.

Abstract: A system for predictive analysis and/or process control, preferably including one or more communication and/or computing systems, and optionally including one or more entities and/or sensors. A method for predictive analysis and/or machine operation, preferably including receiving entity data and determining one or more latent features, and optionally including determining one or more response reconstructions, determining a processed representation of the entity data, determining entity information, and/or acting based on entity information.

Abstract: A system for predictive analysis and/or process control, preferably including one or more communication and/or computing systems, and optionally including one or more entities and/or sensors. A method for predictive analysis and/or machine operation, preferably including receiving entity data and determining one or more latent features, and optionally including determining one or more response reconstructions, determining a processed representation of the entity data, determining entity information, and/or acting based on entity information.

Abstract: A system for predictive analysis and/or process control, preferably including one or more communication and/or computing systems, and optionally including one or more entities and/or sensors. A method for predictive analysis and/or machine operation, preferably including receiving entity data and determining one or more latent features, and optionally including determining one or more response reconstructions, determining a processed representation of the entity data, determining entity information, and/or acting based on entity information.

Abstract: A system for predictive analysis and/or process control, preferably including one or more communication and/or computing systems, and optionally including one or more entities and/or sensors. A method for predictive analysis and/or machine operation, preferably including receiving entity data and determining one or more latent features, and optionally including determining one or more response reconstructions, determining a processed representation of the entity data, determining entity information, and/or acting based on entity information.

Abstract: A system for predictive analysis and/or process control, preferably including one or more communication and/or computing systems, and optionally including one or more entities and/or sensors. A method for predictive analysis and/or machine operation, preferably including receiving entity data and determining one or more latent features, and optionally including determining one or more response reconstructions, determining a processed representation of the entity data, determining entity information, and/or acting based on entity information.

Abstract: Via redundancy insertion is described. A via layout is analyzed by identifying each via, and for each via, identifying a location therefore in the layout, whether the via is redundant and a layout configuration for the via. Each via is classified into a bin of similar layout configurations. For each bin of redundant vias, possible via replacement candidates are determined from a database of possible replacement vias, and the candidates are ranked according to rule-based, recommendation-based and/or model-based criteria. For each via in each bin having a replacement(s), an optimal replacement is identified from among the ranked candidates taken in ranked order that first satisfies another criteria, such as not violating an applicable design rule. The layout is then updated with the optimal replacement.

Abstract: Via redundancy insertion is described. A via layout is analyzed by identifying each via, and for each via, identifying a location therefore in the layout, whether the via is redundant and a layout configuration for the via. Each via is classified into a bin of similar layout configurations. For each bin of redundant vias, possible via replacement candidates are determined from a database of possible replacement vias, and the candidates are ranked according to rule-based, recommendation-based and/or model-based criteria. For each via in each bin having a replacement(s), an optimal replacement is identified from among the ranked candidates taken in ranked order that first satisfies another criteria, such as not violating an applicable design rule. The layout is then updated with the optimal replacement.

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Abstract: Methodologies and an apparatus enabling an improvement of a manufacturing yield of an IC design are disclosed. Embodiments include: determining a portion of a layout of an IC design, the portion including a first pattern including a plurality of design connections; determining a function performed by the first pattern based, at least in part, on the design connections; and selecting, by a processor, a second pattern based on the function.

Abstract: An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs.

Abstract: An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs.

Abstract: Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.

Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

Abstract: Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.

Abstract: A method and system for designing an optimized specification of an integrated circuit (IC) is provided. The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method includes preparing a linewidth map of at least one device of the plurality of devices, performing a topography-aware analysis of the at least one device based on the linewidth map, and designing the optimized specification of the IC based on the topography-aware analysis. In another embodiment, a method for estimating a leakage power of at least one device in an IC is provided. The method includes determining a defocus and a pitch value, determining a linewidth value based on the defocus and pitch value, and estimating the leakage current and/or leakage power based on the linewidth value.