Patents by Inventor Swapneel Kekre

Swapneel Kekre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8214834
    Abstract: A system for asynchronous process sleep or wake management and corresponding methods thereof are described. The system comprises a sleep queue hash table, a process, and a first sleep object and a second sleep object. The first and second sleep objects each comprise a sleep queue and each of the first and second sleep objects are associated with the process. The system further comprises one or more kernel-space processes arranged to perform at least one of associating the first sleep object with the sleep queue hash table and designating the second sleep object to be used for sleeping the process.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: July 3, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Vasudevan Sangili, Chukwuma Valentine Akpuokwe, Swapneel Kekre
  • Patent number: 8032884
    Abstract: Systems, methods, and devices, including computer executable instructions for transferring threads are described. The method comprises determining an idle processor by checking a handoff state of the processor prior to placing an identified runnable thread in a run queue of an idle processor. The method also comprises transferring the runnable thread to a determined idle processor by setting the handoff state of the processor to a handle of the runnable thread.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: October 4, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Harshadrai Parekh, Colin Edward Honess, Douglas V. Larson, Swapneel Kekre
  • Patent number: 7793293
    Abstract: An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: September 7, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Scott J. Norton, Hyun J. Kim, Swapneel Kekre
  • Patent number: 7743383
    Abstract: A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: June 22, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Scott J. Norton, Hyun J. Kim, Swapneel Kekre
  • Publication number: 20080270812
    Abstract: A system for asynchronous process sleep or wake management and corresponding methods thereof are described. The system comprises a sleep queue hash table, a process, and a first sleep object and a second sleep object. The first and second sleep objects each comprise a sleep queue and each of the first and second sleep objects are associated with the process. The system further comprises one or more kernel-space processes arranged to perform at least one of associating the first sleep object with the sleep queue hash table and designating the second sleep object to be used for sleeping the process.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Vasudevan Sangili, Chukwuma Valentine Akpuokwe, Swapneel Kekre
  • Publication number: 20080104593
    Abstract: Systems, methods, and devices, including computer executable instructions for transferring threads are described. The method comprises determining an idle processor by checking a handoff state of the processor prior to placing an identified runnable thread in a run queue of an idle processor. The method also comprises transferring the runnable thread to a determined idle processor by setting the handoff state of the processor to a handle of the runnable thread.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Harshadrai Parekh, Colin Edward Honess, Douglas V. Larson, Swapneel Kekre
  • Publication number: 20060168254
    Abstract: An arrangement, in a computer system, for coordinating scheduling of threads on a processor associated with a scheduling-enabled entity. The arrangement includes a policy database of scheduling policies. The arrangement further includes an automatic policy selector associated with the scheduling-enabled entity. The automatic policy selector is configured to automatically select one of the scheduling policies responsive to a triggering event that includes at least one of a first event and a second event. The first event represents a change in configuration of the scheduling-enabled entity and the second event represents a policy selection from a human operator. One of the scheduling policies is employed to schedule the threads on the processors after being selected by the automatic policy selector.
    Type: Application
    Filed: November 1, 2004
    Publication date: July 27, 2006
    Inventors: Scott Norton, Hyun Kim, Swapneel Kekre
  • Publication number: 20060095909
    Abstract: A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Scott Norton, Hyun Kim, Swapneel Kekre
  • Publication number: 20060095908
    Abstract: An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Scott Norton, Hyun Kim, Swapneel Kekre
  • Publication number: 20060020701
    Abstract: Apparatus and methods are provided for transferring threads. One embodiment of a computing device includes a number of processors including a first processor, a memory in communication with the at least one of the number of processors, and computer executable instructions stored in memory and executable on at least one of the number of processors. The computer executable instructions include instructions to select a second processor, wherein the selection is based upon proximity of the second processor to the first processor. Computer executable instructions also include instructions to select a thread for transfer from the second processor and transfer the selected thread from the second processor to the first processor.
    Type: Application
    Filed: March 7, 2005
    Publication date: January 26, 2006
    Inventors: Harshadrai Parekh, Swapneel Kekre