Abstract: Aspects relate to a stepped clocking frequency mode for integrated circuit components. An apparatus includes a processor core configured to perform operations at a received clocking frequency and a clock controller. The clock controller is configured to clock the processor core with a default frequency in response to the processor core operating in a default mode of operation, and, responsive to a parameter value associated with the processor core exceeding a first threshold, to enter a stepped clocking frequency mode, that includes alternating between clocking the processor core at a first frequency for a first time interval, and clocking the processor core at a second frequency different than the first frequency for a second time interval.

Abstract: Aspects relate to a stepped clocking frequency mode for integrated circuit components. An apparatus includes a processor core configured to perform operations at a received clocking frequency and a clock controller. The clock controller is configured to clock the processor core with a default frequency in response to the processor core operating in a default mode of operation, and, responsive to a parameter value associated with the processor core exceeding a first threshold, to enter a stepped clocking frequency mode, that includes alternating between clocking the processor core at a first frequency for a first time interval, and clocking the processor core at a second frequency different than the first frequency for a second time interval.