Patents by Inventor Swathi G

Swathi G has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tests for integrated circuit (IC) chips
    Patent number: 11994559
    Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: May 28, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lakshmanan Balasubramanian, Rubin Parekhji, Kalyan Chakravarthi Chekuri, Swathi G
  • TESTS FOR INTEGRATED CIRCUIT (IC) CHIPS
    Publication number: 20230143500
    Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.
    Type: Application
    Filed: July 22, 2022
    Publication date: May 11, 2023
    Inventors: Lakshmanan Balasubramanian, Rubin Parekhji, Kalyan Chakravarthi Chekuri, Swathi G