Patents by Inventor Swayam PATTNAIK

Swayam PATTNAIK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual tap architecture for enabling secure access for DDR memory test controller
    Patent number: 11037651
    Abstract: Disclosed are methods and apparatus for securely accessing and testing a double data rate (DDR) memory device. The apparatus includes a first memory test access port (TAP) configured to enable or disable access to at least one double date rate (DDR) memory device, a second memory TAP configured to enable or disable access to at least one non-DDR memory device, and a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP. In an aspect, at least one non-DDR memory device contains proprietary information. Accordingly, access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 15, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Arvind Jain, Anju George, Swayam Pattnaik
  • DUAL TAP ARCHITECTURE FOR ENABLING SECURE ACCESS FOR DDR MEMORY TEST CONTROLLER
    Publication number: 20200143902
    Abstract: Disclosed are methods and apparatus for securely accessing and testing a double data rate (DDR) memory device. The apparatus includes a first memory test access port (TAP) configured to enable or disable access to at least one double date rate (DDR) memory device, a second memory TAP configured to enable or disable access to at least one non-DDR memory device, and a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP. In an aspect, at least one non-DDR memory device contains proprietary information. Accordingly, access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 7, 2020
    Inventors: Arvind JAIN, Anju GEORGE, Swayam PATTNAIK