Patents by Inventor Swee Cheng

Swee Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080099539
    Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.
    Type: Application
    Filed: October 17, 2007
    Publication date: May 1, 2008
    Inventors: Cheng Tay, Pek Tan, Swee Cheng, Eng Yap
  • Publication number: 20070102817
    Abstract: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.
    Type: Application
    Filed: December 26, 2006
    Publication date: May 10, 2007
    Inventors: Cheng Tay, Swee Cheng, Eng Goh
  • Patent number: 7208967
    Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Swee Cheng Ho, Teik Sean Toh, Tzyy Haw Tan
  • Patent number: 7129729
    Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Swee Cheng Ho, Teik Sean Toh, Tzyy Haw Tan
  • Publication number: 20060091188
    Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Cheng Tay, Pek Tan, Swee Cheng, Eng Yap
  • Patent number: 6956387
    Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: October 18, 2005
    Assignee: Intel Corporation
    Inventors: Swee Cheng Ho, Teik Sean Toh, Tzyy Haw Tan
  • Publication number: 20040262368
    Abstract: A method, system, and apparatus are provided for improving ball grid array (BGA) joint reliability. According to one embodiment, an area of weakness in a BGA package having an array of solder balls is determined, and a bonder is applied to the area of weakness independently of the array of solder balls.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 30, 2004
    Inventors: Tan Tzyy Haw, Toh Teik Sean, Ho Swee Cheng