Patents by Inventor Swee-chin Pang

Swee-chin Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for adaptive power management based on processor utilization and cache misses
    Patent number: 7814485
    Abstract: A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: October 12, 2010
    Assignee: Intel Corporation
    Inventors: Bryan C Morgan, Premanand Sakarda, Priya N Vaidya, Yi Ge, Zhou Gao, Swee-chin Pang, Manoj I Thadani, Canhui Yuan
  • Dynamic TLB locking based on page usage metric
    Patent number: 7082508
    Abstract: A translation look-aside buffer (TLB) has lockable entries. A number of entries to lock may be determined by counting unique page access instances during an active period of a process, determining a value of a page usage metric for the process, and comparing the value of the page usage metric to values of page usage metrics for other processes. The page usage metric may consider many different factors, including the amount of time a process is active, a frequency of invocation of the process, and a priority level of a process.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: July 25, 2006
    Assignee: Intel Corporation
    Inventors: Moinul H. Khan, Swee-chin Pang
  • System and method for adaptive power management
    Publication number: 20060123253
    Abstract: A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.
    Type: Application
    Filed: December 7, 2004
    Publication date: June 8, 2006
    Inventors: Bryan Morgan, Premanand Sakarda, Priya Vaidya, Yi Ge, Zhou Gao, Swee-chin Pang, Manoj Thadani, Canhui Yuan
  • Dynamic TLB locking
    Publication number: 20040268071
    Abstract: A translation look-aside buffer (TLB) has lockable entries. TLB entries may be locked to make them available to a process during more than one active period.
    Type: Application
    Filed: June 24, 2003
    Publication date: December 30, 2004
    Applicant: Intel Corporation
    Inventors: Moinul H. Khan, Swee-Chin Pang