Patents by Inventor Swee Hock Lim

Swee Hock Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7477662
    Abstract: A data switch 1 includes a switching engine 7, and input/output interfaces 5 which each connect the switching engine 7 to one of a number of channels. The input/output interfaces 5 and the switching engine 7 are each made up of a number of modules (PHY, MAC_RX, RX, MAC_TX, TX, PBM, ARL, QM). Some or all of the modules have a logic circuit for turning them on when they are required to process data packets passing through the circuit, and a logic circuit is provided for turning them off when they are no longer required. In this way the power requirements of the switch 1 are reduced.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: January 13, 2009
    Assignee: Infineon Technologies AG
    Inventors: Swee Hock Lim, Hong Lee Koo
  • Publication number: 20060047754
    Abstract: A mailbox (5) is proposed for transferring data between two processors (1, 3). The mailbox (5) includes a main memory (7) and an ancillary memory (13, 15). The mailbox stores received data packets in the main memory (7), and stores in the ancillary memory (13, 15) those data packets which are to be read out soonest. In response to a read signal, the mailbox (5) transmits data from the ancillary memory (13, 15) and replenishes the ancillary memory (7) by transferring data to it from the main memory (7). This means that the mailbox (5) can transmit data on the clock cycle following reception of the read signal.
    Type: Application
    Filed: November 15, 2002
    Publication date: March 2, 2006
    Applicant: Infineon Technologies AG
    Inventors: Ramkrishnan Wenkata Subramanian, Swee Hock Lim, Gulam Mohamed
  • Publication number: 20050093006
    Abstract: An LED array arrangement that reduces the number of control inputs needed to operate it is described. The reduction in the number of control pins is achieved through the use of logical ‘AND’ decoding and multiplexing of the control input signals.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 5, 2005
    Inventors: Swee Hock Lim, Jasmeet Narang
  • Patent number: 6822968
    Abstract: A method and apparatus for reducing link latency caused by logic in a network interface. A media access controller having a converter, modification logic, a FIFO and a controller reduces the link latency caused when the logic modifies a data packet. The converter receives frame data from a transmit buffer and converts the frame data into a data packet having a prescribed format for transmission onto a network. The logic modifies the data packet. The FIFO buffers the data packet using a plurality of flip-flops. The controller controls the flow of the data packet and determines when to transmit the data packet onto a network via a media access controller.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: November 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Alvin Swee Hock Lim
  • Publication number: 20040160898
    Abstract: A data switch 1 includes a switching engine 7, and input/output interfaces 5 which each connect the switching engine 7 to one of a number of channels. The input/output interfaces 5 and the switching engine 7 are each made up of a number of modules (PHY, MAC_RX, RX, MAC_TX, TX, PBM, ARL, QM). Some or all of the modules have a logic circuit for turning them on when they are required to process data packets passing through the circuit, and a logic circuit is provided for turning them off when they are no longer required. In this way the power requirements of the switch 1 are reduced.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Applicant: Infineon Technologies AG
    Inventors: Swee Hock Lim, Hong Lee Koo
  • Patent number: 6704364
    Abstract: A network interface that can converts frame data into a data packet which is sent from one local area network to another local area network in which the two local area networks operate using different prescribed network protocols. The network interface receives frame data from a transmit buffer and converts the frame data into a first data packet having a first prescribed network protocol and where the data packet includes first CRC digits. Logic converts the first data packet into a converted data packet having a second prescribed network protocol, which is different than the first prescribed network protocol. The converted data packet also includes second CRC digits which were generated based on the converted data packet at well as being generated by the same CRC generator that generated the first CRC digits.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: March 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alvin Swee Hock Lim, Jeffrey Dwork
  • Patent number: 6539520
    Abstract: An Internet hardware description code generation system, methods, and scripts are provided. The Internet hardware description code generation system includes a hardware description code generation host adapted to generate one or more hardware description language files in response to one or more input parameters. A user uploads input parameters corresponding to a circuit to the hardware description code host. In response, the host generates one or more hardware description language (HDL) files that describe the circuit. Cgi scripts may be used to generate the HDL files.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: March 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Spencer Hao Tiong, Alvin Swee Hock Lim