Patents by Inventor Swee Kwang Chua
Swee Kwang Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100096737Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: Micron Technology, Inc.Inventor: Swee Kwang Chua
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Patent number: 7674655Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.Type: GrantFiled: November 1, 2007Date of Patent: March 9, 2010Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia
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Patent number: 7553697Abstract: A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: November 9, 2006Date of Patent: June 30, 2009Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 7485562Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: January 3, 2005Date of Patent: February 3, 2009Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Publication number: 20080211113Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: ApplicationFiled: May 13, 2008Publication date: September 4, 2008Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo
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Patent number: 7375009Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.Type: GrantFiled: August 28, 2002Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo
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Patent number: 7304375Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.Type: GrantFiled: September 7, 2005Date of Patent: December 4, 2007Assignee: Micron Technology, Inc.Inventors: Suan Jeung Boon, Yong Poo Chia, Siu Waf Low, Meow Koon Eng, Swee Kwang Chua, Shuang Wu Huang, Yong Loo Neo, Wei Zhou
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Patent number: 7274094Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.Type: GrantFiled: August 28, 2002Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventors: Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low
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Patent number: 7193312Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.Type: GrantFiled: September 7, 2005Date of Patent: March 20, 2007Assignee: Micron Technology, Inc.Inventors: Suan Jeung Boon, Yong Poo Chia, Siu Waf Low, Meow Koon Eng, Swee Kwang Chua, Shuang Wu Huang, Yong Loo Neo, Wei Zhou
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Patent number: 7173330Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: June 30, 2005Date of Patent: February 6, 2007Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 7112471Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.Type: GrantFiled: October 23, 2003Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low
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Patent number: 7087992Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: November 30, 2004Date of Patent: August 8, 2006Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Patent number: 6987031Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: August 27, 2002Date of Patent: January 17, 2006Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 6964881Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: August 27, 2002Date of Patent: November 15, 2005Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Patent number: 6958537Abstract: A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: August 4, 2004Date of Patent: October 25, 2005Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Publication number: 20050116337Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: January 3, 2005Publication date: June 2, 2005Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou
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Patent number: 6882021Abstract: Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, the device includes an image sensor die having a first side with a bond-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at the first side of the image sensor die and a lead mounted to the second side of the image sensor die. The window is radiation transmissive and positioned over the active area of the image sensor die. The lead is electrically coupled to the bond-pad on the image sensor die.Type: GrantFiled: August 29, 2003Date of Patent: April 19, 2005Assignee: Micron Technology, Inc.Inventors: Suan Jeung Boon, Yong Poo Chia, Min Yu Chan, Meow Koon Eng, Siu Waf Low, Swee Kwang Chua
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Publication number: 20040238909Abstract: Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, the device includes an image sensor die having a first side with a bond-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at the first side of the image sensor die and a lead mounted to the second side of the image sensor die. The window is radiation transmissive and positioned over the active area of the image sensor die. The lead is electrically coupled to the bond-pad on the image sensor die.Type: ApplicationFiled: August 29, 2003Publication date: December 2, 2004Inventors: Suan Jeung Boon, Yong Poo Chia, Min Yu Chan, Meow Koon Eng, Siu Waf Low, Swee Kwang Chua
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Patent number: 6825553Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: September 5, 2003Date of Patent: November 30, 2004Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Publication number: 20040229400Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: ApplicationFiled: June 22, 2004Publication date: November 18, 2004Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Shuangwu Huang, Wei Zhou