Abstract: There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: There is provided an interpolation circuit of an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals sequentially have a 90 degrees phase shift and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Abstract: An interpolation circuit comprising: a phase shift circuit, configured to generate a plurality of phase shift signals; a first multiplexer configured to receive at least portion of the phase shift signals; a first comparator, comprising a first positive input terminal and a first negative input terminal; a second comparator, comprising a second positive input terminal and a second negative input terminal; a first state control circuit, configured to control the first multiplexer to switch to a different state according to a first comparing result and a second comparing result, wherein the first multiplexer outputs different ones of the phase shift signals in different states; and a first voltage level compensating circuit, configured to pull up or pull down a first output signal from the first output terminal or a second output signal from the second output terminal when the state of the first multiplexer changes.

Abstract: An interpolation circuit comprising: a phase shift circuit, configured to generate a plurality of phase shift signals; a first multiplexer configured to receive at least portion of the phase shift signals; a first comparator, comprising a first positive input terminal and a first negative input terminal; a second comparator, comprising a second positive input terminal and a second negative input terminal; a first state control circuit, configured to control the first multiplexer to switch to a different state according to a first comparing result and a second comparing result, wherein the first multiplexer outputs different ones of the phase shift signals in different states; and a first voltage level compensating circuit, configured to pull up or pull down a first output signal from the first output terminal or a second output signal from the second output terminal when the state of the first multiplexer changes.

Abstract: There is provided an interpolation circuit of an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals sequentially have a 90 degrees phase shift and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: There is provided an interpolation circuit of an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals sequentially have a 90 degrees phase shift and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Abstract: There is provided an interpolation circuit of an optical encoder including a phase shifter circuit, two multiplexers. two digital circuits and four comparators. The phase shifter circuit receives signals sequentially have a 90 degrees phase shift and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Abstract: There is provided a BJT pixel circuit including a BJT transistor, a photodiode, a first storage capacitor and a second storage capacitor. The first storage capacitor is configured to discharge, via the BJT transistor, to a first output voltage in a first exposure time of the photodiode. The second storage capacitor is configured to discharge, via the BJT transistor, to a second output voltage in a second exposure time of the photodiode.

Abstract: The present invention discloses an image processing method and an image processing system adopting the same. The method includes the steps of: (a) obtaining a pixel array representing an image; (b) segmenting the pixel array into two or more non-overlapping regions; (c) identifying a capacitor discharging rate of each of the regions; (d) generating a pulse width modulation (PWM) signal when a voltage level dropping of a capacitor exceeds a predetermined threshold; and (e) applying exposure parameters to the regions according to the capacitor discharging rate of the regions, respectively, wherein the exposure parameter applied to one of the regions is different from the exposure parameter applied to at least another one of the regions.

Abstract: A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.