Patents by Inventor Swee Tuck Woo
Swee Tuck Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8664708Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.Type: GrantFiled: February 25, 2013Date of Patent: March 4, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
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Patent number: 8664711Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: GrantFiled: September 5, 2013Date of Patent: March 4, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun Jung, Swee Tuck Woo, Sanford Chu, Liang Choo Hsia
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Patent number: 8659067Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.Type: GrantFiled: February 25, 2013Date of Patent: February 25, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
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Publication number: 20140001538Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun JUNG, Swee Tuck WOO, Sanford CHU, Liang Choo HSIA
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Patent number: 8541273Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: GrantFiled: September 23, 2010Date of Patent: September 24, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun Jung, Swee Tuck Woo, Sanford Chu, Liang Choo Hsia
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Patent number: 8383476Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.Type: GrantFiled: September 23, 2010Date of Patent: February 26, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
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Patent number: 8383475Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.Type: GrantFiled: September 23, 2010Date of Patent: February 26, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Sung Mun Jung, Kian Hong Lim, Jianbo Yang, Swee Tuck Woo, Sanford Chu
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Publication number: 20120262985Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with a primary gate and forming a charge storage layer on the substrate over the primary gate. A secondary gate electrode layer is formed on the substrate over the charge storage layer. The charge storage and secondary gate electrode layers are patterned to form first and second secondary gates on first and second sides of the primary gate.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Applicant: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.Inventors: Ying Qian WANG, Yu CHEN, Swee Tuck WOO, Bangun INDAJANG, Sung Mun JUNG
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Publication number: 20120074483Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sung Mun JUNG, Kian Hong LIM, Jianbo YANG, Swee Tuck WOO, Sanford CHU
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Publication number: 20120074537Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sung Mun JUNG, Swee Tuck WOO, Sanford CHU, Liang Choo HSIA
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Publication number: 20120074482Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sung Mun JUNG, Kian Hong LIM, Jianbo YANG, Swee Tuck WOO, Sanford CHU
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Publication number: 20100013003Abstract: An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu CHEN, Donghua LIU, Sung Mun JUNG, Swee Tuck WOO, Rachel LOW, Louis LIM, Siow Lee CHWA
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Patent number: 7595237Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.Type: GrantFiled: April 27, 2007Date of Patent: September 29, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu Chen, Donghua Liu, Sung Mun Jung, Swee Tuck Woo, Rachel Low, Louis Lim, Siow Lee Chwa
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Publication number: 20080266944Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaoyu Chen, Donghua Liu, Sung Mun Jung, Swee Tuck Woo, Rachel Low, Louis Lim, Siow Lee Chwa
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Patent number: 7332378Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.Type: GrantFiled: March 4, 2006Date of Patent: February 19, 2008Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sung Mun Jung, Ching Dong Wang, Louis Yoke Leng Lim, Swee Tuck Woo, Donghua Liu, Xiaoyu Chen
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Publication number: 20070207558Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.Type: ApplicationFiled: March 4, 2006Publication date: September 6, 2007Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sung Mun Jung, Ching Dong Wang, Louis Yoke Leng Lim, Swee Tuck Woo, Donghua Liu, Xiaoyu Chen