Patents by Inventor Sweetesh Singh

Sweetesh Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190332300
    Abstract: A fingerprint trie is used to store fingerprints for data portions stored on a storage system for use in implementing data deduplication on a storage system. The fingerprint trie may be used to compare fingerprint values to determine duplicate data portions, for example, in response to I/O operations. Leaf nodes of the fingerprint trie may be keyed by fingerprints, and a value of each leaf node may be a reference to the physical storage location of the data portion from which the fingerprint was generated. When an I/O operation is received, a fingerprint may be generated for each of one or more data portions included in the I/O operation. A fingerprint trie may be searched, for example by traversing multiple nodes of the trie according to pointers provided by the nodes, to determine whether there is any matching fingerprint specified in the fingerprint trie.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Applicant: EMC IP Holding Company LLC
    Inventor: Sweetesh Singh
  • Patent number: 10140161
    Abstract: A method of workload aware dynamic CPU processor core allocation includes the steps of predicting estimated individual workloads for each emulation in a set of emulations for each decision period of a set of decision periods over a predictive time span. The method includes using, by a Mixed Integer Programming (MIP) engine, the predicted estimated individual workloads for each emulation in the set of emulations, a set of constraints, and an optimization function, to determine sets of CPU processor cores to be allocated to each emulation during each decision period over the predictive time span. The method further includes dynamically allocating, by the host computer system, the sets of CPU processor cores to each emulation during each decision period over the predictive time span based on the output from the MIP engine.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: November 27, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Sweetesh Singh, Ashish Kamra