Patents by Inventor Sy Vo

Sy Vo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230335218
    Abstract: The present invention relates to a self-designed single-nucleotide polymorphism chip and a method of computing polygenic risk score (PRS) for a given population using the self-designed single-nucleotide polymorphism chip. The self-designed single-nucleotide polymorphism chip using LmTag algorithm comprises the following modules: a pairwise imputation score computation module; a functional score computation module; and a tag SNP selection module.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Applicant: GENESTORY Joint Stock Company
    Inventors: Tham Hong Hoang, Giang Minh Vu, Dat Thanh Nguyen, Trang Thi Ha Tran, Vinh Chi Duong, Nam Sy Vo
  • Patent number: 7132700
    Abstract: A disclosed embodiment is a method for fabricating a structure in a semiconductor die, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: November 7, 2006
    Assignee: Newport Fab, LLC
    Inventors: Gregory D. U'Ren, Sy Vo
  • Patent number: 6861308
    Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: March 1, 2005
    Assignee: Newport Fab, LLC
    Inventors: Gregory D. U'Ren, Sy Vo
  • Publication number: 20040227157
    Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.
    Type: Application
    Filed: May 13, 2003
    Publication date: November 18, 2004
    Applicant: Newport Fab, LLC dba Jazz Semiconductor
    Inventors: Gregory D. U'Ren, Sy Vo