Patents by Inventor Syamal Kumar Lahiri

Syamal Kumar Lahiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7419905
    Abstract: A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si1-x—Gex alloy, Ge and mixtures thereof and a layer of metal of thickness tm; and annealing the layers, such that substantially all of the first material and the metal are consumed during reaction with one another.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: September 2, 2008
    Assignee: Agency for Science, Technology and Research
    Inventors: Dominique Mangelinck, Dongzhi Chi, Syamal Kumar Lahiri
  • Patent number: 7137830
    Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: November 21, 2006
    Assignee: NanoNexus, Inc.
    Inventors: Syamal Kumar Lahiri, Frank Swiatowiec, Fu Chiung Chong, Sammy Mok, Erh-Kong Chieh, Roman L. Milter, Joseph M. Haemer, Chang-Ming Lin, Yi-Hsing Chen, David Thanh Doan
  • Patent number: 7126220
    Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: October 24, 2006
    Assignee: NanoNexus, Inc.
    Inventors: Syamal Kumar Lahiri, Frank Swiatowiec, Fu Chiung Chong, Sammy Mok, Erh-Kong Chieh, Roman L. Milter, Joseph M. Haemer, Chang-Ming Lin, Yi-Hsing Chen, David Thanh Doan
  • Patent number: 7015132
    Abstract: A method of constructing an electrical contact on an electronic component comprises first forming a protruding electrically conducting stud at a contact location by wire bonding a metal wire to a contact pad of the component. The stud is then contacted with solder, without using a mask, so that a solder bump is deposited on and adheres to the metal stud to form a composite solder contact which is able to form with a contact of another component a solder joint which has good electrical and mechanical properties and which may be reliable fabricated at high density by a low cost method. An electronic component provided with such solder contacts and an electronics component package including such a component are also disclosed.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: March 21, 2006
    Assignee: Agency for Science, Technology and Research
    Inventors: Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah
  • Patent number: 6917525
    Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: July 12, 2005
    Assignee: NanoNexus, Inc.
    Inventors: Sammy Mok, Fu Chiung Chong, Frank John Swiatowiec, Syamal Kumar Lahiri, Joseph Michael Haemer
  • Publication number: 20030218244
    Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.
    Type: Application
    Filed: March 17, 2003
    Publication date: November 27, 2003
    Inventors: Syamal Kumar Lahiri, Frank Swiatowiec, Fu Chiung Chong, Sammy Mok, Erh-Kong Chieh, Roman L. Milter, Joseph M. Haemer, Chang-Ming Lin, Yi-Hsing Chen, David Thanh Doan
  • Publication number: 20030214045
    Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.
    Type: Application
    Filed: March 17, 2003
    Publication date: November 20, 2003
    Inventors: Syamal Kumar Lahiri, Frank Swiatowiec, Fu Chiung Chong, Sammy Mok, Erh-Kong Chieh, Roman L. Milter, Joseph M. Haemer, Chang-Ming Lin, Yi-Hsing Chen, David Thanh Doan
  • Publication number: 20030099097
    Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.
    Type: Application
    Filed: June 24, 2002
    Publication date: May 29, 2003
    Inventors: Sammy Mok, Fu Chiung Chong, Frank John Swiatowiec, Syamal Kumar Lahiri, Joseph Michael Haemer
  • Patent number: 6531396
    Abstract: A method of fabricating a silicide layer on a silicon region of a semiconductor structure, the method comprising the steps of: providing a semiconductor structure having at least one silicon region on a surface thereof; depositing a layer comprising nickel and platinum on the at least one silicon layer; annealing the semiconductor structure and the nickel/platinum layer to react the nickel and the platinum with underlying silicon to form a nickel-platinum silicide, wherein annealing step takes place at temperature of between 680° C. and 720° C.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: March 11, 2003
    Assignee: Institute of Materials Research and Engineering
    Inventors: Dongzhi Chi, Syamal Kumar Lahiri, Dominique Mangelinck
  • Publication number: 20020102745
    Abstract: A method of modifying a chip assembly substrate comprising the steps of:
    Type: Application
    Filed: August 2, 2001
    Publication date: August 1, 2002
    Applicant: Institute of Materials Research & Engineering
    Inventors: Syamal Kumar Lahiri, Harvey Monroe Phillips
  • Publication number: 20020102765
    Abstract: A method of constructing an electrical contact on an electronic component comprises first forming a protruding electrically conducting stud at a contact location by wire bonding a metal wire to a contact pad of the component. The stud is then contacted with solder, without using a mask, so that a solder bump is deposited on and adheres to the metal stud to form a composite solder contact which is able to form with a contact of another component a solder joint which has good electrical and mechanical properties and which may be reliable fabricated at high density by a low cost method. An electronic component provided with such solder contacts and an electronics component package including such a component are also disclosed.
    Type: Application
    Filed: January 2, 2002
    Publication date: August 1, 2002
    Inventors: Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah
  • Patent number: 6214642
    Abstract: An area array flip chip device produced using wire bonding technology. The design and process for producing such a flip chip involves stud bumps which are bonded on the substrate, to give good electrical interconnections between the chip pads and the substrate pads. This completely eliminates the limitation of not being able to have stud bump interconnections over the active area of the chip, and allows the stud bump interconnection method to be applied over the entire chip area. The design and process can also be applied to the joining of a substrate or first level packaging to the board. In this embodiment, the stud bump process acts as a replacement for the BGA process.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: April 10, 2001
    Assignee: Institute of Materials Research and Engineering
    Inventors: William T. Chen, Syamal Kumar Lahiri