Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract: A package for a semiconductor integrated circuit die comprises a redistributed layer formed over a first barrier layer electrically connected to a bonding pad of a die. A second barrier layer is formed over the redistributed layer. A multi-metal layer is formed over the second barrier layer for coupling to a solder ball, wherein the multi-metal layer has an extending part that extends outside a second opening over the upper of the second dielectric layer to prevent tin infiltration from the solder ball to the redistribution layer.

Abstract: The present invention relates to semiconductor devices. More specifically, the invention discloses the use of dummy structures to improve thermal conductivity, reduce dishing and strengthen layers formed with low dielectric constant materials.

Abstract: An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.

Abstract: A method of forming an interconnect structure using a low dielectric constant material as an intralayer dielectric is described. In one embodiment, the present inventive method comprises the following steps. A conductive structure that is surrounded by a low dielectric constant material on its side surfaces is formed. A first inorganic insulator is formed over at least a portion of the low dielectric constant material. A second inorganic insulator is formed over the first inorganic insulator. A photoresist layer is deposited and then patterned to form an unlanded via in the second inorganic insulator. The second inorganic insulator and a portion of the first inorganic insulator are etched in order to form the unlanded via.

Abstract: An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.

Abstract: A high density, low capacitance, interconnect structure for microelectronic devices has unlanded vias formed with organic polymer intralayer dielectric material having substantially vertical sidewalls. A method of producing unlanded vias includes forming a planarized organic polymer intra-layer dielectric between conductors, forming an inorganic dielectric over the conductor and organic polymer layer, patterning a photoresist layer such that openings in the photoresist layer overlap portions of both the conductor and the intra-layer dielectric, etching the inorganic dielectric and then concurrently stripping the photoresist and anisotropically etching the organic polymer intra-layer dielectric. A second conductor is typically deposited into the via opening so as to form an electrical connection to the first conductor. A silicon based insulator containing an organic polymer can alternatively be used to form the intra-layer dielectric.