Abstract: A silicon carbide transistor (10) is formed from a silicon carbide film (14) that is formed on a silicon carbide substrate bulk (37). A conductor pattern layer (25) is formed on the silicon carbide film (14) and the silicon carbide film (14) removed from the silicon carbide substrate bulk (37) and attached to a substrate (11) of a dissimilar semiconductor material.

Abstract: A method of fabricating a semiconductor device on thinned wide bandgap material including providing a support having a planar surface and a semiconductor substrate. Implanting a layer of ions in the substrate to create a layer of microbubbles defining a thin film having a planar surface and a remaining mass separated by the layer of implanted ions. Intimately contacting the planar surface of the thin film to the planar surface of the support and heating the support and substrate to separate the remaining mass from the thin film. A semiconductor device is formed on the thin film, and the support is thinned.

Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: An integrated circuit substrate (26) is formed with active circuit elements (24, 32) on first and second surfaces of the substrate. The active circuit elements are interconnected with though-substrate vias (28) to minimize signal routing and reduce propagation delay. The through-substrate vias may be formed with a plurality of holes (52) through the IC substrate. A dielectric layer (54) is deposited on the surface of the IC substrate and through the holes. A conductive layer (56) is deposited through the holes to form the through-substrate vias. The dielectric layer is removed from the surface of the IC substrate to leave the through-substrate vias isolated from the IC substrate by the dielectric layer. A second substrate (26) is formed as described and the two substrates are joined as a two-sided chip (21) with active circuit elements on both sides interconnected by through-substrate vias.

Abstract: A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.

Abstract: A method of fabricating a trench structure includes providing a substrate having a first layer disposed on a surface thereof and a second layer disposed on the first layer. A trench is formed through the first and second layers and into the substrate. A dielectric liner is formed on the sidewalls of the trench which is then filled with a trench fill material. Portions of the trench liner disposed above the trench fill material are removed and a conformal layer is then formed on the trench structure. The conformal layer and a portion of the trench fill material are then oxidized.

Abstract: A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer is formed over a bottom interconnect layer, and an interlayer dielectric is formed on the sacrificial layer. A via is etched in the interlayer dielectric, exposing the sacrificial layer. The sacrificial layer is isotropically etched to expose an area of the interconnect metal that is larger than the area of the via and a via metallization is selectively formed on the interconnect metal by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer, is filled with the via metallization, thereby providing a contact area to the bottom interconnect metal which is larger than the via metallization itself.

Abstract: A method for determining silicon mass 28 beam purity prior to implanting gallium arsenide by implanting silicon in a silicon monitor wafer and analyzing the damage created by the implantation.

Abstract: Implantation of oxygen or nitrogen in polysilicon layers to a dose above about 10.sup.15 ions/cm.sup.2 retards rapid grain boundary migration of conventional dopants such as B, P, As, Sb, and the like during dopant activation. Pre-annealing of the poly films to increase the grain size also decreases rapid grain boundary migration. The effects can be combined by first pre-annealing and then implanting oxygen or nitrogen before introducing the dopant. It is desirable to anneal the oxygen implant before introducing the dopant to allow for oxygen diffusion to the grain surfaces where it precipitates and blocks the grain boundaries. Vertical and lateral migration of the dopants can be inhibited by placing the implanted oxygen or nitrogen between the dopant and the location desired to be kept comparatively free of dopants. When very high dopant activation temperatures are used the blocking effect of the oxygen on the grain boundaries is overwhelmed by dopant diffusion through the grains.

Abstract: Hillock formation as a result of heating uncapped polycrystalline silicon layers can be avoided by first implanting the uncapped poly layers with silicon, oxygen, or nitrogen prior to heating. Equivalent mono-atomic oxygen or nitrogen doses in the range of about 10.sup.15 to about 5.times.10.sup.16 ions/cm.sup.2 at energies in the range 10-50 keV are useful with good results being obtained with equivalent oxygen doses of 2.times.10.sup.15 ions/cm.sup.2 at 30 keV. When polysilicon layers with this oxygen implant are heated to about 1150 degrees C., a temperature which would ordinarily produce pronounced hillock formation in un-capped, un-treated poly layers, it is found that hillock formation is suppressed. The implanted oxygen concentrations are far below what is required to produce a separate oxide layer or phase. Some effect on poly layer sheet resistance is observed for implanted oxygen but the implanted layers have sheet resistances within a factor of two of those without the oxygen implants.

Abstract: Zener diodes and other semiconductor junctions having very low noise characteristics and improved yield may be obtained by first ion implanting a suitable impurity into a substrate wafer, and then forming the p-n junction using a very rapid thermal activation and annealing process. For p-n junctions formed with boron (.sup.11 B) implanted into n-type silicon to a peak concentration exceeding 10.sup.20 atoms/cm.sup.3, the rapid activation process comprises heating from about room temperature to about 1150.degree. C. in 12-30 seconds, and then cooling back below 1000 degrees C. in less than 5 seconds. Noise voltages measured on devices formed using the invented process were typically much lower and more narrowly grouped than on devices of the prior art. Dynamic impedance was also slightly reduced.

Abstract: A method for diffusing a metal dopant into a semiconductor switching device is provided by the use of a rapid thermal heating apparatus. This method provides a procedure for the selectively placing of a metal dopant in a region of the device or circuit. This aids in increasing the manufacturing yields of the switching device, and increases the number of active traps for minority carriers.

Abstract: MOS transistors in which the source and drain contact are isolated from the common substrate are formed by using the gate conductor to mask a high dose high energy implant which creates a thin dielectric region within the body of the common substrate beneath the source and drain regions, but not beneath the channel region. For single crystal silicon substrates, oxygen and nitrogen are the preferred ions for use in forming the buried dielectric region. The conductive gate must be sufficiently thick so as to preclude the implanted oxygen or nitrogen ions from reaching the underlying gate dielectric or the portion of and channel region of the device will be substantially free the substrate beneath the gate. This ensures that the gate and channel region of the device will be substantially free of the implant damage which otherwise occurs during formation of the buried dielectric regions. Dielectric isolation walls are conveniently provided laterally exterior to the source-drain regions.

Abstract: Implantation of oxygen or nitrogen in polysilicon layers to a dose above about 10.sup.15 ions/cm.sup.2 retards rapid grain boundary migration of conventional dopants such as B, P, As, Sb, and the like during dopant activation. Pre-annealing of the poly films to increase the grain size also decreases rapid grain boundary migration. The efffects can be combined by first pre-annealing and then implanting oxygen or nitrogen before introducing the dopant. It is desirable to anneal the oxygen implant before introducing the dopant to allow for oxygen diffusion to the grain surfaces where is precipitates and blocks the grain boundaries. Vertical and lateral migration of the dopants can be inhibited by placing the implanted oxygen or nitrogen between the dopant and the location desired to be kept comparatively free of dopants. When very high dopant activation temperatures are used the blocking effect of the oxygen on the grain boundaries is overwhelmed by dopant diffusion through the grains.

Abstract: Gate current leakage is reduced in a submicron FET device by the deposition of an oxide layer over the gate prior to the rapid heating of the device. This is done to prevent the dopant that was implanted into the gate from collecting on the sidewalls of the gate and the oxide layer between gate and substrate. Otherwise the diffused dopant becomes the path of least resistance, thus creating current leakage from the gate to source or gate to drain.

Abstract: A means and method is described for shielding semiconductor charge storage devices from the effects of particles or ionizing radiation absorbed within the bulk of the semiconductor substrate, by providing a free carrier shield consisting of a buried layer of very low lifetime in the undisturbed material below the depletion regions associated with the charge storage devices. The very low lifetime layer is obtained by ion implantation of a super-saturated zone of impurities such as oxygen which provide deep recombination centers and which react chemically with the substrate material so as to provide thermally stable complexes which do not anneal away during post implant heating cycles. Concentrations of lifetime killing impurities significantly exceeding the solid solubility limit are achieved so that the lifetime reduction in the carrier shield region greatly exceeds that obtainable by prior art methods.