Abstract: A method for high performance caching is disclosed. The method generally includes steps (A) and (B). Step (A) may fetch a plurality of reference samples of a reference image from a first circuit to a cache of a second circuit. The cache may include a plurality of cache blocks and a plurality of valid bits. Each of the cache blocks generally corresponds to at most one of the valid bits. A size of the cache blocks may match a smallest read access size of the first circuit. Step (B) may transfer the reference samples having the corresponding valid bit set to valid from the cache to a processor of the second circuit.

Abstract: An apparatus including a local shared memory and a processor. The local shared memory and the processor may be connected as a circuit. The local shared memory may comprise a plurality of cache blocks. Each of the cache blocks generally corresponds to one of a plurality of panes of a current horizontal strip of a warped image region to be generated from unwarped image data retrieved from an external source. The circuit may be further configured such that each pixel of the unwarped image data retrieved from the external source is fetched only once. Each of the panes has associated tag information.

Abstract: An apparatus including a local shared memory and a processor. The local shared memory and the processor may be connected as a circuit. The circuit may be configured to communicate with an external memory device. The local shared memory may comprise a plurality of cache blocks. Each of the cache blocks generally corresponds to one pane of a current horizontal strip of a warped image region to be generated from unwarped image data stored in the external memory. A size of the cache blocks may be set to provide a sufficient amount of data to correct distortion for a corresponding section of the current horizontal strip. The circuit may be further configured such that each pixel of the unwarped image data stored in the external memory is fetched only once.

Abstract: A method for high performance caching is disclosed. The method generally includes steps (A) and (B). Step (A) may fetch a plurality of reference samples of a reference image from a first circuit to a cache of a second circuit. The cache may include a plurality of cache blocks and a plurality of valid bits. Each of the cache blocks generally corresponds to at most one of the valid bits. A size of the cache blocks may match a smallest read access size of the first circuit. Step (B) may transfer the reference samples having the corresponding valid bit set to valid from the cache to a processor of the second circuit.