Abstract: An apparatus includes an electromagnetic which supports propagation of an electromagnetic wave in a first direction between a first end thereof and a second end thereof, and an electromagnetic-field shaping structure within the electromagnetic waveguide. The electromagnetic-field shaping structure defines a channel extending from a first aperture in a first wall of the apparatus to a second aperture in a second, opposite, wall. The channel has an axis extending in a second direction which is nonparallel with the first direction. The distance between the first aperture and the second aperture in the second direction is less than the width of the interior region of the waveguide at the first and second ends thereof. In some embodiments, a plasma torch is disposed within the channel. The length of the torch closely matches its interaction region.

Abstract: An apparatus includes an electromagnetic which supports propagation of an electromagnetic wave in a first direction between a first end thereof and a second end thereof, and an electromagnetic-field shaping structure within the electromagnetic waveguide. The electromagnetic-field shaping structure defines a channel extending from a first aperture in a first wall of the apparatus to a second aperture in a second, opposite, wall. The channel has an axis extending in a second direction which is nonparallel with the first direction. The distance between the first aperture and the second aperture in the second direction is less than the width of the interior region of the waveguide at the first and second ends thereof. In some embodiments, a plasma torch is disposed within the channel. The length of the torch closely matches its interaction region.

Abstract: A feature phone has two processors that share a display. The display is attached to an applications processor that has a frame buffer for refreshing the display. A base-band processor also runs programs that generate graphics data that is written to a base-band frame buffer. Updates to the base-band frame buffer are sent through a shared-memory interface to a shared memory, and a shared mailbox is written with the message length, triggering a mailbox-interrupt to the applications processor. The applications processor reads the message from the shared memory and updates a copied frame buffer. An overlay engine uses the copied frame buffer to refresh the display when the base-band processor has the focus, or to refresh a smaller base-band window that covers a portion of the display, leaving the rest of the display area for applications-processor graphics data. Rapid switching between the copied and local frame buffer is possible.

Abstract: A feature phone has two processors that share a key pad for user input. The key pad is attached to a base-band processor and sends an interrupt to a user-hardware-interrupt UHI driver running on the base-band processor when the user presses a key. When a hot switch indicates that the local base-band processor has the focus, a key-press event is sent to the local kernel to be sent to programs on the base-band processor. When the hot switch indicates that a remote applications processor has the focus, a message for the event is written through a shared-memory interface to a shared memory on the applications processor. A shared mailbox is written with the message length, triggering a mailbox-interrupt to the applications processor. A virtual UHI driver running on the applications processor reads the event message from the shared memory and passes key-press information to programs on the applications processor.

Abstract: The properties of features formed in a substrate are measured. Lenslet array illumination is used to illuminate regions of a substrate so that the features of interest occupy a greater proportion of the illuminated area. The signal-to-noise ratio of the measurement signal is therefore increased, and the sensitivity of the measurement is thus improved.

Abstract: A microprocessor having an architecture for pipelining instructions to reduce the time necessary to execute sequential instructions including an arithmetic and logic unit for processing information; a register file for storing data to be used by the arithmetic and logic unit, the register file including individual registers from which data is read for operations by the arithmetic and logic unit and to which data is written which results from operations of the arithmetic and logic unit; and apparatus for obtaining updated data from a source other than the register file when sequential instructions processed by the arithmetic and logic unit change data in a particular register in the register file during a first instruction and then use the data in the register file which was changed in a second instruction so that the data in the particular register is stale at the time it is required for the second instruction.

Abstract: Apparatus for increasing the decoding speed of a microprocessor. The apparatus includes a first decoder for decoding macroinstructions. The first decoder includes apparatus for generating a single initial microinstruction vector from simple macroinstructions and from complex macroinstructions having a beginning microinstruction equivalent to a microinstruction for a simple macroinstruction. The first decoder also includes apparatus for indicating a beginning address for generating any remaining microinstruction vectors for a complex macroinstruction decoded by the first decoder. The apparatus for increasing the decoding speed of a microprocessor also includes apparatus, coupled to the first decoder, for generating any remaining microinstruction vectors for complex macroinstructions decoded by the first decoder. The apparatus for generating any remaining microinstruction vectors includes apparatus for responding to the apparatus for indicating a beginning address.

Abstract: In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, and apparatus for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement including apparatus for detecting the appearance of a particular prefixed instruction, apparatus responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, apparatus in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and apparatus for generating a request to the microcontroller to handle microcode vectors generated.

Abstract: In a circuit for accomplishing arithmetic operations and including an ALU; a first register for holding a dividend to be divided and intermediate and final results of the operation; a second register for holding a divisor; and apparatus for sequentially causing the dividend to be shifted left by one bit and the divisor subtracted from or added to the highest order bits of the dividend and partial remainders to provide a result which determines a quotient bit and thereby practice the operation of non-restore division, the improvement including: apparatus for performing an XNOR operation on the result of any carryout from any addition or subtraction operation and the value of the highest order bit of the dividend or the partial remainder; and apparatus for providing the result of the XNOR operation as the quotient bit to the arithmetic and logic unit.