Patents by Inventor Syed Alam

Syed Alam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN
    Publication number: 20070287224
    Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
    Type: Application
    Filed: April 19, 2007
    Publication date: December 13, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATION
    Inventors: Syed Alam, Ibrahim Elfadel, Kathryn Guarini, Meikei Ieong, Prabhakar Kudva, David Kung, Mark Lavin, Arifur Rahman
  • Semiconductor stacked die/wafer configuration and packaging and method thereof
    Publication number: 20070057384
    Abstract: A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 15, 2007
    Inventors: Syed Alam, Robert Jones, Scott Pozder
  • Three dimensional integrated circuit and method of design
    Publication number: 20060033110
    Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 16, 2006
    Inventors: Syed Alam, Ibrahim Elfadel, Kathryn Guarini, Meikei Ieong, Prabhakar Kudva, David Kung, Mark Lavin, Arifur Rahman