Patents by Inventor Syed Ali Jafri

Syed Ali Jafri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10133678
    Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 20, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Yasuko Eckert, Syed Ali Jafri, Srilatha Manne, Gabriel Loh
  • Patent number: 9710392
    Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: July 18, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Syed Ali Jafri, Yasuko Eckert, Srilatha Manne, Mithuna S Thottethodi
  • Patent number: 9378153
    Abstract: A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. The modified data is stored in the set in a cache line with an eviction priority that is at least as high as an eviction priority, before the modified data is stored, of an unmodified cache line with a highest eviction priority among unmodified cache lines in the set.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 28, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Syed Ali Jafri, Yasuko Eckert, Srilatha Manne
  • Publication number: 20160049181
    Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 18, 2016
    Inventors: Syed Ali Jafri, Yasuko Eckert, Srilatha Manne, Mithuna S. Thottethodi
  • Publication number: 20150067264
    Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Yasuko Eckert, Syed Ali Jafri, Srilatha Manne, Gabriel Loh
  • Publication number: 20150067266
    Abstract: A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. The modified data is stored in the set in a cache line with an eviction priority that is at least as high as an eviction priority, before the modified data is stored, of an unmodified cache line with a highest eviction priority among unmodified cache lines in the set.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Syed Ali Jafri, Yasuko Eckert, Srilatha Manne