Patents by Inventor Syed Arsalan Jawed

Syed Arsalan Jawed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10727796
    Abstract: The invention provides a Low-voltage Differential Signaling (LVDS) receiver circuit that comprises a folded-cascode operational transconductance amplifier (OTA) that includes a pair of input branches and a pair of output branches. The pair of input branches of the folded-cascode OTA includes a p-channel metal-oxide semiconductor (PMOS) input transistor pair connected to a first supply voltage domain. The pair of output branches includes an output circuit connected to a second supply voltage domain. The LVDS receiver circuit further includes a common-mode feedback circuit connected to the pair of output branches of the folded-cascode OTA that controls the second supply voltage domain. The LVDS receiver circuit further includes a regenerative buffer circuit connected to the pair of output branches of the folded-cascode OTA and an output generated from the pair of output branches of the folded-cascode OTA directly operates the regenerative buffer circuit to produce a distortion-free output signal.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 28, 2020
    Assignee: THE KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY (KACST)
    Inventors: Mohammed Sulaiman BenSaleh, Syed Arsalan Jawed, Yasir Mehmood Siddiqi, Waqas Siddiqi, Shahab Ahmed Najmi
  • Publication number: 20190348958
    Abstract: The invention provides a Low-voltage Differential Signaling (LVDS) receiver circuit that comprises a folded-cascode operational transconductance amplifier (OTA) that includes a pair of input branches and a pair of output branches. The pair of input branches of the folded-cascode OTA includes a p-channel metal-oxide semiconductor (PMOS) input transistor pair connected to a first supply voltage domain. The pair of output branches includes an output circuit connected to a second supply voltage domain. The LVDS receiver circuit further includes a common-mode feedback circuit connected to the pair of output branches of the folded-cascode OTA that controls the second supply voltage domain. The LVDS receiver circuit further includes a regenerative buffer circuit connected to the pair of output branches of the folded-cascode OTA and an output generated from the pair of output branches of the folded-cascode OTA directly operates the regenerative buffer circuit to produce a distortion-free output signal.
    Type: Application
    Filed: August 17, 2016
    Publication date: November 14, 2019
    Applicant: The King Abdulaziz City for Science and Technology
    Inventors: Mohammed Sulaiman BenSaleh, Syed Arsalan Jawed, Yasir Mehmood Siddiqi, Waqas Siddiqi, Shahab Ahmed Najmi
  • Patent number: 9785178
    Abstract: A current reference generator includes a first voltage reference configured to generate a first current through a first resistor; a second voltage reference configured to generate a second current; a first current mirror configured to subtract the second current from the first current to generate a temperature invariant current; a third voltage reference configured to generate a third current via a second resistor; and a second current mirror configured to: subtract the temperature invariant current from the third current to produce a process-temperature invariant current, and output the process-temperature invariant current.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 10, 2017
    Assignee: KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Mohammed Sulaiman BenSaleh, Syed Arsalan Jawed, Yasir Mehmood Siddiqi, Abdulfattah Mohammad Obeid, Ahmed Kassem, Shahab Ahmed Najmi, Syed Manzoor Qasim
  • Publication number: 20170269624
    Abstract: A current reference generator includes a first voltage reference configured to generate a first current through a first resistor; a second voltage reference configured to generate a second current; a first current mirror configured to subtract the second current from the first current to generate a temperature invariant current; a third voltage reference configured to generate a third current via a second resistor; and a second current mirror configured to: subtract the temperature invariant current from the third current to produce a process-temperature invariant current, and output the process-temperature invariant current.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: Mohammed Sulaiman BenSaleh, Syed Arsalan Jawed, Yasir Mehmood Siddiqi, Abdulfattah Mohammad Obeid, Ahmed Kassem, Shahab Ahmed Najmi, Syed Manzoor Qasim
  • Publication number: 20090322353
    Abstract: In a capacitive sensor, a detection structure, of a microelectromechanical type, is provided with a fixed element and a mobile element, capacitively coupled to one another, generating a capacitive variation as a function of a quantity to be detected, and with a parasitic coupling element, capacitively coupled to at least one between the mobile element and the fixed element generating a first parasitic capacitance, intrinsic to the detection structure; a readout-interface circuit is connected to the detection structure and generates, on an output terminal thereof, an output signal as a function of the capacitive variation. The readout-interface circuit has a feedback path between the output terminal and the parasitic coupling element so as to drive the first intrinsic parasitic capacitance with the output signal.
    Type: Application
    Filed: April 29, 2008
    Publication date: December 31, 2009
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Tommaso Ungaretti, Syed Arsalan Jawed, Massimo Gottardi, Andrea Baschirotto