Abstract: Systems and methods for obtaining corrected time information in a GPS-enabled device connected to a mobile handset via a short-range wireless network, such as a Bluetooth™ Piconet™. The mobile handset includes a GPS time and a network clock synchronized with a network clock in a short-range wireless network interface in the GPS-enabled device. The GPS-enabled device may send requests for time information to the mobile handset. The mobile handset receives the request and latches the network clock time and the GPS time. The captured network clock time and GPS times are sent to the GPS-enabled device in response to the request. The GPS-enabled device subtracts the captured network clock time from its own network clock time and adds the difference to the captured GPS time to obtain a corrected GPS time.

Abstract: Systems and methods for obtaining corrected time information in a GPS enabled device connected to a mobile handset via a short-range wireless network, such as a Bluetooth Piconet. The mobile handset includes a GPS time and a network clock synchronized with a network clock in a short-range wireless network interface in the GPS enabled device. The GPS enabled device may send requests for time information to the mobile handset. The mobile handset receives the request and latches the network clock time and the GPS time. The captured network clock time and GPS times are sent to the GPS enabled device in response to the request. The GPS enable device substracts the captured network clock time from its own network clock time and adds the difference to the captured GPS time to obtain a corrected GPS time.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.