Patents by Inventor Syed Naseef

Syed Naseef has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12112091
    Abstract: Systems and methods for unifying multiple audio bus interfaces in an audio system are disclosed herein. In one aspect, an integrated circuit (IC) comprises a primary slave audio device comprising a first control circuit, and a dependent slave audio device comprising a second control circuit. The primary slave audio device and the dependent slave audio device are communicatively coupled via a slave status link, and the first control circuit and the second control circuit each configured to receive, from a master audio device, a mode instruction that indicates operation in one of a detach mode and a unify mode. The second control circuit is configured to, while operating in the detach mode, transmit a slave status to the master audio device via a second control lane, and, while operating in the unify mode, transmit the slave status to the primary slave audio device via the slave status link.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: October 8, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Syed Naseef, David Belz
  • Publication number: 20240296009
    Abstract: Systems and methods for unifying multiple audio bus interfaces in an audio system are disclosed herein. In one aspect, an integrated circuit (IC) comprises a primary slave audio device comprising a first control circuit, and a dependent slave audio device comprising a second control circuit. The primary slave audio device and the dependent slave audio device are communicatively coupled via a slave status link, and the first control circuit and the second control circuit each configured to receive, from a master audio device, a mode instruction that indicates operation in one of a detach mode and a unify mode. The second control circuit is configured to, while operating in the detach mode, transmit a slave status to the master audio device via a second control lane, and, while operating in the unify mode, transmit the slave status to the primary slave audio device via the slave status link.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 5, 2024
    Inventors: Syed Naseef, David Belz
  • Patent number: 11487495
    Abstract: Systems and methods for essentially continuous audio flow for Internet of Things (IoT) devices during power mode transitions contemplate an audio bus, such as a SOUNDWIRE audio bus, to maintain an audio stream during a clock transition without having to tear down the audio stream as a new clock becomes active on the audio bus. By preserving the audio stream during such a transition, gaps in the audio are avoided resulting in better performance and end user experience.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: November 1, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Nileena Pathalayi Alakandy, Syed Naseef
  • Publication number: 20220261207
    Abstract: Systems and methods for essentially continuous audio flow for Internet of Things (IoT) devices during power mode transitions contemplate an audio bus, such as a SOUNDWIRE audio bus, to maintain an audio stream during a clock transition without having to tear down the audio stream as a new clock becomes active on the audio bus. By preserving the audio stream during such a transition, gaps in the audio are avoided resulting in better performance and end user experience.
    Type: Application
    Filed: February 12, 2021
    Publication date: August 18, 2022
    Inventors: Lior Amarilio, Nileena Pathalayi Alakandy, Syed Naseef
  • Publication number: 20190087369
    Abstract: Full-duplex memory access systems and methods for improved quality of service (QoS) are disclosed. In one aspect, a primary bus owner will evaluate an output from a secondary bus owner when the primary bus owner takes control of the bus to determine if the secondary bus owner has data to send to the primary bus owner and/or is in the midst of a bulk data transfer. If the evaluation determines that there is still data to be transferred, the primary bus owner may refrain from draining an internal register unless a full word is present in the register. By reducing memory access for a partial word in the register, QoS may be improved.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 21, 2019
    Inventors: Lior Amarilio, Syed Naseef, Ghanashyam Prabhu